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The code is simply doing nothing, because the output pwm isn't set anywhere in the code. Synthesizes to nothing (0 LEs).
A complete pwm unit would have a duty cycle input. if (counter<=256) should be changed to if (counter >= 255) for reasonable counter operation.module pwm1(clk,pwm);
input clk;
output pwm;
reg counter=0;
reg pwm;
always @(posedge clk)
begin
counter=counter+1;
If (counter<=256)
counter=0;
end
endmodule
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Verilog is case sensitive, if isn't a legal keyword.
Please consider also that (counter>=256) never happens, because the maximum value of counter is 255.- Mark as New
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Thank you sir
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