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pwm verilog code

Altera_Forum
Honored Contributor II
2,601 Views

Hi, 

 

please help me to fnd pwm Verilog code 

 

thank yu
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Altera_Forum
Honored Contributor II
1,115 Views

Hello, 

 

check this out !  

http://www.ece301.com/fpga-projects/53-pwm.html 

 

REMEMBER : google is your best friend :)
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Altera_Forum
Honored Contributor II
1,115 Views

Hi, 

 

I would like to know whether attached code is right to generate pwm wave.  

 

please reply
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Altera_Forum
Honored Contributor II
1,115 Views

Hi, 

Your code will generate a wave that looks like a PWM !  

To create a PWM you need a duty cycle (how often do you want to refresh your signal) : You need to know your board frequency and compute the duty of your PWM ... 

 

The link I gave you explain that ! Follow the steps and stop jumping into coding something you don't understand  

 

I recommend you read the page carefully
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Altera_Forum
Honored Contributor II
1,115 Views

Hi, 

 

I hope this idea is correct. 

my fpga clock is 50mhz.that is period 20ns. 

I designed a pwm with 1000ns period. 

 

switch variable given as 2 to get 80 percent duty cycle. 

 

please check. 

 

Thankyou
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Altera_Forum
Honored Contributor II
1,115 Views

1000 ns => 

P = 0.000001*50000000 = 50 

SC (Steps Count) = 2^3 = 8 

==> sd = P / SC = 50/8 =6.25 

but you are using sd = 20 ! 

 

Please read carefully the page (link I posted) and follow the steps ! It's not that hard !
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Altera_Forum
Honored Contributor II
1,115 Views

Hi, 

 

what is mean by refreshing signal?? I didn't get. can't i take p=1000ns?
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Altera_Forum
Honored Contributor II
1,115 Views

by refreshing signal we mean the time we need to have a new value (period) 

Yes you can take whatever period you want ! For 1000 ns P = 50 (because you multiply the 20 ns by 50 to get 1000 ns)
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