Automatic IO pin creation

[Altera_Forum]

Hello, 

 to explain my question a short word to my design flow. My designs are written in VHDL except the top level. For better readability toplevel is a schematic .bdf file.  In some design I have a lot of I/O pins on toplevel. Actually I create the pins by "clicking" in editor. Is there a possibility to do this work automatically by reading an input file or via TCL script? To clarify I am looking for a automatic IO pin creating not a pin assignment.  Thank for your help Volker

[Altera_Forum]

--- Quote Start ---   In some design I have a lot of I/O pins on toplevel. Actually I create the pins by "clicking" in editor. Is there a possibility to do this work automatically by reading an input file or via TCL script?   --- Quote End ---    Yes, you can create a Tcl script. Here's the easiest method you can use to get started.  1. Synthesize an existing design that contains pin assignments. 2. Open the Quartus pin planner and confirm that all pins are assigned (no white cells) 3. From the Quartus GUI select "Project->Generate Tcl File for Project"  Now look at the generated Tcl file. That file will contain lines like   set_location_assignment PIN_D1 -to sc_dq set_location_assignment PIN_T7 -to sram_dq set_location_assignment PIN_R1 -to sram_addr set_location_assignment PIN_R14 -to sw set_location_assignment PIN_D6 -to usb_d set_location_assignment PIN_E5 -to sc_resetN set_location_assignment PIN_A7 -to usb_d set_location_assignment PIN_L16 -to pci_ad   Copy those lines to a file called pinout.tcl, and you can use that from that point on to assign pins for that FPGA.  My personal preference for designs is to have all code in VHDL, and to use a top-level VHDL file that always has all top-level ports, whether the design uses them or not. This allows the pinout file to include all pins, and avoids Quartus warnings about ignored assignments. In your BDF design flow, if your top-level design does not include a pin that your pin assignment script assigns, then Quartus will issue warnings about ignored constraints. You can either live with that, or get a little fancier by running a Tcl script during P&R that first finds all the pins in the current design, and then creates the pin assignments for just those pins. You can use pre-flow/post-flow scripts for this type of fine control.  http://www.altera.com/support/examples/tcl/auto_processing.html  Have a play with these ideas, and if you get stuck, come back to the forum and ask for help.  Cheers, Dave

[Altera_Forum]

Thank you Dave, 

 I use the bdf design flow because our SW- and HW guys are more familar with this "schematic look". If I do toplevel design for simulation purpose I also use all VHDL style.  In my opinion your TCL code do the pin assignment of existing pins. e.g IO pin "sc_dq[2] is assigned to FPGA pin D1. What I am looking for is a way to generate IO pins for .bdf toplevel files automatically, so that I can be much faster to do the .bdf  Regards Volker

[Altera_Forum]

Hi Volker, 

  --- Quote Start ---   In my opinion your TCL code do the pin assignment of existing pins. e.g IO pin "sc_dq[2] is assigned to FPGA pin D1. What I am looking for is a way to generate IO pins for .bdf toplevel files automatically, so that I can be much faster to do the .bdf   --- Quote End ---    If I understand correctly, you are asking how to automatically add the pin numbers to the BDF.  I do not use BDF, but the following should work; draw your top-level BDF and use pin names that match your Tcl pin assignments script, then run the script and synthesize the design. The Pin Planner view should show that all the pin assignments match your Tcl script. Re-open the BDF file, and Quartus might also re-annotate the BDF to show the pin numbers. If it does not, its not really a problem, since the Pin Planner shows they are correct.  Cheers, Dave

[Altera_Forum]

Hi Dave  

--- Quote Start ---     If I understand correctly, you are asking how to automatically add the pin numbers to the BDF.  e  --- Quote End ---    No, I am looking for a method to prevent to clicking "insert input" and naming the input like nRESET_Switch for each input /output/bidirektional pin in .bdf file. actually I have to create 176 IO pins on toplevel. The last 10 year I always do these method to make a toplevel in bdf cause my colleagues want to have a schematic look and feel of fpga designfile. Now I am asking me if there is a better like a scripting.  I have tried tcl command "add_new_io" or "make_input_port" but these commands required a compiled toplevel design ( so it seems to me).  The easiest way for me is doing the toplevel in VHDL but this will dissatisfy my colleagues who can not read vhdl :-) Do you know another method to display a vhdl toplevel like a schematic?  Volker

[Altera_Forum]

--- Quote Start ---   No, I am looking for a method to prevent to clicking "insert input" and naming the input like nRESET_Switch for each input /output/bidirektional pin in .bdf file. actually I have to create 176 IO pins on toplevel.   --- Quote End ---   Ah, ok, I understand now.  Have you considered creating a BDF template, where you create the 176 ports on the left-hand-side of a schematic, and then always start with that? You can connect ports to component inputs using named nets, so you would never have to move the ports.    --- Quote Start ---   The last 10 year I always do these method to make a toplevel in bdf cause my colleagues want to have a schematic look and feel of fpga designfile. Now I am asking me if there is a better like a scripting.  I have tried tcl command "add_new_io" or "make_input_port" but these commands required a compiled toplevel design ( so it seems to me).   --- Quote End ---   The problem with any automated method for making a schematic is "where are you going to place the ports?"    --- Quote Start ---   The easiest way for me is doing the toplevel in VHDL but this will dissatisfy my colleagues who can not read vhdl :-) Do you know another method to display a vhdl toplevel like a schematic?   --- Quote End ---   Quartus creates a netlist view of a design; see Tools->Netlist Viewer->RTL Viewer  Show your colleagues this version of the schematic and see if that is acceptable to them. Keep in mind that if you had to write Tcl to create a top-level schematic (BDF), then the arrangement of the ports in this view is about all you could expect ... its not the "prettiest", but it does the job.  This would then allow you to create a top-level VHDL file, making it easier to create your simulations.  Cheers, Dave

[Altera_Forum]

Thanks Dave, 

 in your post there are some interesting thinks I want to try.  Our designs are very application specific, so pin names are often not equal between different projects. But if I create a bdf template with the most used pins, I can copy/paste them in the actual design.  By the way, do you know the function of tcl command "add_new_io" or "make_input_port". Where do they add the pins? to a netlist?  Many thanks Volker

[Altera_Forum]

--- Quote Start ---   Our designs are very application specific, so pin names are often not equal between different projects. But if I create a bdf template with the most used pins, I can copy/paste them in the actual design.   --- Quote End ---   How about making a VHDL top-level that contains *only* a BDF file. That way you could connect your application-specific BDF to a top-level that always has the same pin names.  Alternatively, if the pin names are only one of several names, you could write a "smarter" pin assignments script. I recall writing a test where after design elaboration you can read the top-level pins in a design. You could then compare the list of actual pins, to your pin names list (with multiple names per pin) and then select the appropriate one from the list.    --- Quote Start ---   By the way, do you know the function of tcl command "add_new_io" or "make_input_port". Where do they add the pins? to a netlist?   --- Quote End ---   I've never used them. If I had this same question, I would simply create a new design and try using the Tcl commands.  Cheers, Dave