Signal Tap II display signals?

[Altera_Forum]

Hi, I am new to Quartus II and using SignalTap II.  

How can I set up SignalTap to just capture and display the signals between two times or values? For example, in my code I have an integer counting from 0 to 33 and I would like SignalTap to show me only the signals between those values in one window. Many thanks in advance.

[Altera_Forum]

signaltap much be connected to a clock, and you can set it to trigger on a certain condition. Could you not just set it to wait until the counter is 0? if it doesnt capture enough time you will need to re-compile with a larger window.  

You can also set up multiple cores inside the design and have them trigger at different points.  If you need some more complicated trigger conditions, it is much easier to generate the trigger logic in HDL, use syn_keep and noprune attributes on them and then connect them into signaltap.

[Altera_Forum]

I don't see where are these options tho. If for example I just want to capture the first 100 clock cycles in the window, how do I do this? Thanks

[Altera_Forum]

There should be 3 trigger options: instant, on trigger, or continuous on trigger. 

 Instant takes a snapshot now trigger waits until the trigger occurs, then downloads the buffer continuous on trigger will wait until the trigger condition occurs, download the buffer, then wait for the trigger to occur again. If you set no trigger conditions, it will just keep downloading the buffer (its not a continuous play function, you will miss the data in between the downloads).  You cant just download a specified number of clocks, you need to download the entire buffer.

[Altera_Forum]

Hi, Sorry but I don't see these options. On the right hand side , in the serial configuration section , I see storage qualifier options. I chose start /stop but still doesn't work as I can still just see the instantaneous signals. Down under trigger, there is trigger in and trigger out options. Is it there I set this up? Also, do I increase the number of trigger conditions to more than 1? Thanks for your help and patience.

[Altera_Forum]

So, if you have 13.1, you should see the buttons in this order along the toolbar: 

"Run Analysis" "Autorun Analysis" "Stop Analysis" "read data"  You set the trigger conditions next to the signals you have added to signal tap by right clicking in the trigger conditions column (if single bits) or typing a value (for a bus)

[Altera_Forum]

If you have enabled the more complex triggering you can chose AND, OR or an advanced option for triggering. Otherwise the option is usually just AND.

[Altera_Forum]

--- Quote Start ---  So, if you have 13.1, you should see the buttons in this order along the toolbar: "Run Analysis" "Autorun Analysis" "Stop Analysis" "read data"  You set the trigger conditions next to the signals you have added to signal tap by right clicking in the trigger conditions column (if single bits) or typing a value (for a bus)  --- Quote End ---     Thanks for your help but I have nearly given up at this stage. I have a variable which counts up after after every 100th input clock positive edge and invert another signal (output clock) at that time. I specified the start and stop value for this variable under storage qualifier to be 0 and 200. When i run it , I would expect to see 200 output clock cycles but once again, it only shows the first pulse. What am I doing wrong? It surely shouldn't be this difficult to do such a simple task.

[Altera_Forum]

If you have a signal incrementing every 100 clocks, and you need to capture the counter going from 0-32, you need a 3200 sample window minimum.  

 Have you simulated the design before you compiled it? signaltap is a debug tool, not a verification tool.

[Altera_Forum]

--- Quote Start ---  If you have a signal incrementing every 100 clocks, and you need to capture the counter going from 0-32, you need a 3200 sample window minimum.   Have you simulated the design before you compiled it? signaltap is a debug tool, not a verification tool.  --- Quote End ---     I have a 50 MHz input clock which is assigned to the crystal on the DE0-Nano board. I am using this then in the serial configuration section on the right in SignalTap as the clock. I have divided this clock by 512 in my code and and when a button is pressed, a counter starts to count from 0 to 32 on every positive edge of this clock pulse. I have put this counter in the start and stop storage qualifier from 0 to 32 and when I press the button, I have no idea why it wont show me the counter from 0 to 32 and all the other signals.   I have tested this code on the development board with LEDs etc. and all works fine but I am unable to simply view the signals on SignalTap. What else could I be doing wrong? I have selected 8K as the sample depth also. Thanks

[Altera_Forum]

I'd use start-stop storage qualifier too. I just tried it. It works. Below is my setup. 

 https://www.alteraforum.com/forum/attachment.php?attachmentid=8432   And the capture:  https://www.alteraforum.com/forum/attachment.php?attachmentid=8433   What do you see?  (What do you see in the photo attached in the post? They were re-sized to a ridiculous small resolution :( Original size: http://signaltapit.com/static_data/img/forum/start_stop.gif http://signaltapit.com/static_data/img/forum/start_stop_data.gif)

[Altera_Forum]

In my trigger condition selection, I just have the options basic and advanced. When advanced is selected, It opens up a new window where components can be placed etc. which I don't think is necessary. What are you using for your serial configuration clock on the right hand side of set-up? On mine I am using clock_50 which corresponds to the 50MHz clock on my board. I am not sure if this is correct. 

 I have even created simple frequency divider VHDL code and I still can't get this to work. I have a counter counting up to 50 and then back to 0. I wish to capture just 0 to 10 of this counter. When I press the trigger, which is a negative edge on the push button, it states that it is acquiring post-trigger data and just does nothing.   Here is my code  LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------ ENTITY freq_divider IS PORT ( clock_50 : IN STD_LOGIC; button : IN STD_LOGIC; clk : OUT STD_LOGIC ); END freq_divider; ------------------------------------------------------------------ ARCHITECTURE behaviour OF freq_divider IS SIGNAL count1 : INTEGER:= 0; SIGNAL count2 : INTEGER:= 0; SIGNAL counter : INTEGER:= 0; --SIGNAL bufclk : STD_LOGIC; SIGNAL freq1 : STD_LOGIC; SIGNAL freq2 : STD_LOGIC; SIGNAL freq3 : STD_LOGIC; SIGNAL freq4 : STD_LOGIC; BEGIN --bufclk<= clock_50; PROCESS (clock_50) VARIABLE GO : STD_LOGIC:= '0'; BEGIN IF (button = '0') THEN GO := '1'; END IF; IF (clock_50'EVENT AND clock_50 = '1' ) THEN count1 <= count1 + 1; IF (count1 >= 200) THEN count1<= 0; counter<= counter +1; IF (counter = 50) THEN counter<= 0; END IF; freq1<= NOT(freq1); END IF; END IF; END PROCESS; PROCESS (freq1) BEGIN IF (freq1'EVENT AND freq1 = '1') THEN count2 <= count2 + 1; IF (count2 >= 50) THEN count2<= 0; freq2<= NOT(freq2); clk<=freq2; END IF; END IF; END PROCESS; END behaviour; ---------------------------------------------------------------------------------------------

[Altera_Forum]

That usually occurs when the trigger events are not happening. Are these signals connected to anything except signaltap, that have an effect on an output? if they're not, you will need syn_keep attributes to prevent the synthesisor removing them. 

 NOTE: Dividing clocks like this is not recommended if you are driving other logic with them.

[Altera_Forum]

Thanks again. Now I changed the clock in the serial configuration on the right hand side to a much lower frequency and I can see the signals changing as they should. I was previously using the 50MHz clock for this. 

 My counter signal however which is added as a node is not counting in the window as the signals change. It stays at 00H which is incorrrect. This counter is defined as an integer in the VHDL code. Is there any reason that it is not displaying the counting? I was expecting to see it count to 10 as this is the start and stop storage condition. All the other signals are changing as expected however.

[Altera_Forum]

Has it been removed like I said? it is possible to add signal names from code only for the synthesisor to remove them. If this is the case you're viewing a signal that no longer exists, but you usually get warning for this. 

Having it as an integer is not ideal for signaltap. see if you can find the signal in the "post synthsis" group of registers. As its an integer it will have made the bus 32 bits wide.

[Altera_Forum]

It seems that you are learning.* Figuring things out yourself is part of the learning process.* I am not going to point out anything obvious.* There are a few not so obvious ones I can tell you. 

 1. You need to learn to verify your design in simulator.* That's part of HDL design flow.  2. If you do use SignalTap to verify as a shortcut of avoiding learning to write testbench, you need to start from beginning: verify one counter and register at a time. Don't start from the end without knowing if circuit leading to the final result is correct.* (Often, the tool is working correctly. Think about your error, not the tool.)* You can add all signals to reduce compilation time since your design is small.* In SignalTap, you can leave the storage qualifier feature on, but disable.* Enable/disable it doesn't require you to recompile, a compilation time saver.* You may find that verifying in simulator will be more productive in long run.* Don't take too much shortcut.  3. Don't use that pulse, freq, as the clock, but as a clock enable signal.* In FPGA, it's never a good idea to use gated clock, unless you know compiler can implement it with special hard clock network circuit on the device.* The timing closure with gated clock is hard.* The compiler is getting better at it.* You cannot rely on it still* Designing a fully synchronized design on simple clock is a key to success in FPGA world.* If learning clock divider is not part of objective, you should be using PLL clock divider instead, a hard device feature.  Have fun learning.