Cyclone PLL output clock pin assignment

[Altera_Forum]

Hi, 

I am using Cyclone IV E FPGA. There are four PLLs on the chip at four corners of the chip respectively. My first question, how many off-chip output clocks are there for each dedicated PLL? Second related question, when i assign a PLL clock output, i notice that there are a pair of pins called "PLLx_CLOCKOUTp" and "PLLx_CLOCKOUTn". It is clear that if i use differential signaling as a clock output,there is only one output clock that could be assigned for a PLL. Right? But, how about a single ended output signal? Or, my question is that if i want two clock outputs from the same PLL as two single ended signals respectively, can i assign them on those two pins? that is, for instance, can i assign CLKo1 to pin PLL3_CLOCKOUTp and the other one, CLKo2 to pin PLL3_CLOCKOUTn from one PLL?  Thanks.  Yaoting

[Altera_Forum]

Hi Yaotin: 

 The PLLx_CLOCKOUTp and n outputs can be defined as differenetial or singled ended outputs.   So the PLLx_CLOCKOUT is dedicated PLL's output, which should only be sourced by that PLL which is drivin by a CLKx input pin associated with that PLL.  Not every PLL will always have dedicated PLLx CLOCKOUT's.  Every PLL will have 4 dedicated CLK-in's (Or 2 differential pairs)  So Care should be taken to make sure you are using the correct output pin so all the routing will be optimized.  Depending on the family you can break these rules, but at the cost of jitter performance, and max freqeuency.  In the past I have driven the dedicated clock out's from two various PLL clock outputs independently, but this could be family related as well. You may want to test this and verify it works.  Pete

[Altera_Forum]

Thanks Pete for your reply. 

Still need your clarification to my question. Based on your reply can i suppose each PLL doesn't have more than one clock output? That means if i use PLL3_CLOCKOUTp pin as a single ended output clock i could not use PLL3_CLOCKOUTn as a second clock output from the same PLL3. Right?  Yaoting