Embed sdc constraint in vhdl design file - help needed

[Altera_Forum]

Hi everyone! 

 I'm trying to set a sdc constraint into one of my vhdl design files. I want to constrain a muliticycle path inside that entity and I want it to go with the design file to reuse it in other projects.  I tried to follow the instructions I found here (http://altera.info/support/kdb/solutions/rd05162013_635.html) and in the Ouartus II Handbook (where the link in the text points to), but I can't get it to work. My search for other useful documentation was without results.  What I would do to set that constraint in a .sdc file is: set_multicycle_path -setup -end -from -to 2  What I actually did in my design file is the following:   entity MyEntity is port ( (...) ); end entity; architecture rtl of MyEntity is (...) signal MySignal : std_logic; attribute altera_attribute: string; attribute altera_attribute of MySignal : signal is "-name SDC_STATEMENT set_multicycle_path -from {*SourceEntity:SourceEntity_Inst|*} -to {*TargetEntity:TargetEntity_Inst|*} -setup -end 2"; begin (...) SourceEntity_Inst : SourceEntity port map( (...) InPort => SomeSignal, OutPort => MySignal ); TargetEntity_Inst : TargetEntity port map( (...) InPort => MySignal, OutPort => SomeOtherSignal ); end rtl;  But TimeQuest still finds that failing path.  Any hints? I would be very grateful!  Thanks in advance,   Sören

[Altera_Forum]

Does it work from the separate SDC file or inputting it directly into timequest? I ask this because it may not be a problem with the attribute etc - but maybe the synthesisor removed the registers or the heirarchy isnt the same name and timequest cannot find the start/endpoint. 

 Are there any warnings in timequest about not finding any nets?

[Altera_Forum]

Many thanks for the fast reply! 

 Yes, from the sdc file it is working.  I reviewed the Quartus processing output and found the section where it says "Evaluating HDL-embedded SDC commands". There are a number of commands listed but all of them are from altera megafunctions and none of them is related to my design file. My command from the design file is just not listed. It seems as if it is not processed.

[Altera_Forum]

--- Quote Start ---  Hi everyone!  entity MyEntity is port ( (...) ); end entity; architecture rtl of MyEntity is (...) signal MySignal : std_logic; attribute altera_attribute: string; attribute altera_attribute of MySignal : signal is "-name SDC_STATEMENT set_multicycle_path -from {*SourceEntity:SourceEntity_Inst|*} -to {*TargetEntity:TargetEntity_Inst|*} -setup -end 2"; begin (...) end rtl;     Sören  --- Quote End ---    This is what I got working. entity clbase is generic( ... ); port( ... PowerDown_n : out std_logic ); end entity; architecture arch of clbase is attribute altera_attribute : string; attribute altera_attribute of arch : architecture is "-name SDC_STATEMENT ""set_false_path -to PowerDown_n""" ; ...  I don't have a multicycle_path handy, but I guess (almost sure) that tying the 'attribute' to the 'architecture' and the double quotes to embed the sdc command into the attribute string is what makes it work.

[Altera_Forum]

--- Quote Start ---  This is what I got working.  ...snip..  I don't have a multicycle_path handy, but I guess (almost sure) that tying the 'attribute' to the 'architecture' and the double quotes to embed the sdc command into the attribute string is what makes it work.  --- Quote End ---    Just had a thought, but in your code you tie the attribute to a port that would already exist. In the OPs code technically the entities havent been instantiated yet, so their names may not exist in the name table yet (or whatever altera does with them). Im not entirely sure this is the case, because SDC constraints arent usually applied until fitter or timing stages. But have you tried putting the constraints inside the entities rather than the architecture above?

[Altera_Forum]

--- Quote Start ---  Just had a thought, but in your code you tie the attribute to a port that would already exist. In the OPs code technically the entities havent been instantiated yet, so their names may not exist in the name table yet (or whatever altera does with them). Im not entirely sure this is the case, because SDC constraints arent usually applied until fitter or timing stages. But have you tried putting the constraints inside the entities rather than the architecture above?  --- Quote End ---    The attribute is tied to the Architecture, although tying it to the Entity is also an option. The same technique is used in AHDL files where you can (could as .tdf have gone out of style) add Timing Analyser commands at the top of the file. They only get evaluated after Analysis & Synthesis. E.g: the dcfifo OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;SYNCHRONIZER_IDENTIFICATION=OFF;SYNCHRONIZATION_REGISTER_CHAIN_LENGTH = 3;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=d103;suppress_da_rule_internal=R105;{-to rdemp_eq_comp_lsb_aeb} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rdemp_eq_comp_lsb_aeb} POWER_UP_LEVEL=HIGH;{-to rdemp_eq_comp_msb_aeb} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to rdemp_eq_comp_msb_aeb} POWER_UP_LEVEL=HIGH;{-to rs_dgwp_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrfull_eq_comp_lsb_mux_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrfull_eq_comp_msb_mux_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;{-to wrptr_g} suppress_da_rule_internal=S102;{-to wrptr_g} POWER_UP_LEVEL=LOW;{-to ws_dgrp_reg} SYNCHRONIZER_IDENTIFICATION=FORCED_IF_ASYNCHRONOUS;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe_re9:dffpipe17|dffe18a;-name SDC_STATEMENT ""set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_re9:dffpipe17|dffe18a* "";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe_qe9:dffpipe14|dffe15a;-name SDC_STATEMENT ""set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_qe9:dffpipe14|dffe15a* """;   even has constraints for both TAn and TQ.   Also moving the multicycle_path exception into the (lower) entities is not possible as the exception targets both entities.

[Altera_Forum]

--- Quote Start ---  ...snip...  I don't have a multicycle_path handy, but I guess (almost sure) that tying the 'attribute' to the 'architecture' and the double quotes to embed the sdc command into the attribute string is what makes it work.  --- Quote End ---    Yes, you were right. That made it work. At least almost. I tried that approach before but I always got error messages from quartus. Obviously I made a syntactical mistake. I guess it was something with the double quotes...  So it works much better now than before but I still don't get the same result as with the .sdc file. The corrected line looks like this now:  attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_multicycle_path -setup -end -from -to 2""";  That makes TimeQuest not longer show that failing path but a slightly different one. It goes from SourceEntity (exactly as it did before) to TargetEntity. But the "To node" is somewhere else in the TargetEntity and the value of the slack changed as well. How could that happen? Even though I put a wildcard behind TargetEntity_Inst?  I did some testing and found out that if I write the whole path from top level to SourceEntity and TargetEntity into the sdc statement (as I did in the .sdc file) it works exactly like in the .sdc file. But that of course is useless for the purpose of reusability of that design file. I expected that the statement affects only MyEntity and Entities below and that everything above MyEntity ist not of interest for the statement. In Quartus Handbook I found that:     --- Quote Start ---  Example 16–121 through Example 16–123 use the altera_attribute to disable the Auto Shift Register Replacement synthesis option for an entity. To apply the Altera Attribute to a VHDL entity, you must set the attribute on its architecture rather than on the entity itself.  --- Quote End ---    That confirms my assumption. Otherwise "Auto Shift Register Replacement" synthesis option would be disabled for the whole design. But obviously I understood something wrong...