FPGA external reset

[Altera_Forum]

hi， 

I am using Cyclone III,and I'd like to have my own external reset.but I am not sure when to safely insert external reset ASAP.  Do I have to use it after CONF_DONE goes high? if it is used before CONF_DONE goes high,Is there a conflict with FPGA configuration ?for the reset IC used for external reset is also POR output.  from the handbook, all I/O are tri-stated when configuration,but my understanding is "all I/O are tri-stated" means FPGA doesn't drive out,but can't block external input,right?    BTW,AS configuration scheme used.    thanks

[Altera_Forum]

Hi There! 

 If you have a reset controller that can monitor the CONF_DONE pin, you should be fine. Another would be to determine how long the configuration time takes. I did this with an EPF10k10, which came in somewhere around 300ms. I then used a standard reset-controller that would pull reset low for about 500ms, well exceeding the 300ms configuration time. Once the FPGA is configured, you'd just have a 500ms reset controller.  Hope this helps,  -Mux

[Altera_Forum]

Hi，Mux， 

thanks for your suggestion, I know from your answer there are two ways to do so. One is to apply external reset after CONF_DONE goes high. Another is to start the external reset(POR) even when configuration, but need to make sure the low external reset time is longer than the configuration.   Is it a potential issue when external reset starts but configuration is not finished. or how to understand the all the I/O are tri-stated when configuration, as I indicated above. thanks.

[Altera_Forum]

A "standard" technique that I picked up from somewhere (perhaps an Altera reference design) was to route CONF_DONE to the reset supervisor input pin via a buffer (to isolate CONF_DONE), eg., see p95 

 http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf http://www.ovro.caltech.edu/~dwh/carma_board/  This ensures that the external reset is asserted until after the device enters user mode.  Cheers, Dave

[Altera_Forum]

If the reset supervisor has a pin for that :-) I used a cheapo TO-92...

[Altera_Forum]

--- Quote Start ---  If the reset supervisor has a pin for that :-) I used a cheapo TO-92...  --- Quote End ---   Sure, for an existing design you can't really do much, but for a new design, its a nicer way to ensure your FPGA is held in reset until it enters user mode.  NOTE: you still need reset synchronizers internal to the FPGA for each of your clock domains.  Cheers, Dave

[Altera_Forum]

Mux and Dave,thanks a lot. it's a new design,I plan to route CONF_DONE to reset supervisor manual input. The "standard" gives me more confidence:_),although I noted http://www.ovro.caltech.edu/~dwh/car...0.87_dec03.pdf is mentioned several times in different threads. 

 I still want to figure out how to understand "all I/O are tri-stated when configuration", Does it mean external POR can't enter FPGA when configuration, or it enters,but has no effect on FPGA configuration? can you help with this?