I do have Quartus 13.1 and a Cyclone 5 project where I do use the same core block several times, basic all RTL does works fine.
So does the project when it loaded into the FPGA
So have the core running fast and also have space for as many cores on the chip as possible I do use the LogicLock for each core and do place them in the ChipPlanner to be symmetrical placed and have the same numbers of ALM and M10K inside each.
When you compile the project and you have lets say 16 cores (doing the exect same job) the numbers og ALM are not the same on each core and some will fit insside the regionlock and other not... and it does change form compile to compile.
I would like to make one core working and the copy it to other location without and change in the lolic by he compiler ...how?
When you assign a core as a design partition, I would expect to be able to reuse it as a 100% clone
Please advise
