Qsys Errors : Master _bridge.tristate_master

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Qsys Errors : Master _bridge.tristate_master

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Hi. I have a some problem. I made a system using tristate_bridge between Master and Slave. But it makes errors like below. Error: System.epc_w_0.s0: Master SOPC_mgt_epc_bridge.tristate_master does not have a waitrequest signal. Slave must match master's read and write wait time (read:0 write:0)It makes me crazy. I thought that Avalon MM Tristate bridge has a problem and tried fix it. But It doesn't have read and write wait time option tab also waitrequest. All user components that I made is same Errors. Please, could you tell me some solution or guys thinking. Anything is good for me. I'm using Version Quartus 13.0sp1. Thanks.

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