Giving external input to Triple Speed Ethernet

[Altera_Forum]

Hello everybody, 

 I want to modify the tutorial "using Triple Speed Ethernet" according to my requirement. In brief what I used is: Qsys(Hardware Generation), NIOS II Eclipse(ApplicationSoftware: C/C++), Wireshark(to see the output in PC coming through Ethernet Interface) and Networking (Ctr+shift+Alt: to see the Link Speed, which is 770 Mbps).  Input is defined within application C/C++ Program in NIOS II Eclipse software as transmitted frame.  I would like to know if I have to give continuous data stream from some pins of FPGA (or after some processing in FPGA) as input to ethernet, what should I do?  I see Conduit Connection in used tse_mac IP core of Qsys. I also see conduit connection in top level generated verilog code. should I modify the generated verilog code in this top level entity to give input and again compile the program or is there any other method?  - Regards FPGA beginner

[Altera_Forum]

The TSE uses two Avalon Stream interfaces for Ethernet packets: a source with received packets and a sink for packets to transmit. Usually in a design with a Nios II CPU and a software layer with a TCP/IP stack, those two interfaces are connected to SGDMAs in QSys. If you do it that way and have the correct software solution, then you can directly send and receive packets through the software API. 

If you need a higher bandwidth you can also make your own IP and connect it to the avalon stream interfaces in QSys instead of the DMAs and generate packets directly there.

[Altera_Forum]

--- Quote Start ---   Usually in a design with a Nios II CPU and a software layer with a TCP/IP stack, those two interfaces are connected to SGDMAs in QSys. If you do it that way and have the correct software solution, then you can directly send and receive packets through the software API.  --- Quote End ---   Hi, I didn't get the point: send and receive packets through the software API. which API software can be used in this case?    --- Quote Start ---    If you need a higher bandwidth you can also make your own IP and connect it to the avalon stream interfaces in QSys instead of the DMAs and generate packets directly there.  --- Quote End ---    yes, I need higher bandwidth 750 Mbps+. In attachment, there is screenshot of how I connect SGDMAs to other components in Qsys. If I remove this SGDMAs, where exactly I have to connect (to the avalon stream interfaces) from own IP.

[Altera_Forum]

--- Quote Start ---  If I remove this SGDMAs, where exactly I have to connect (to the avalon stream interfaces) from own IP.  --- Quote End ---    You would connect to the "transmit" and "receive" Avalon Streaming ports of the TSE MAC.  See this page: http://www.alterawiki.com/wiki/nios_ii_udp_offload_example  In that example, IP blocks are connected in addition to the SGDMA (through the packet multiplexer/demultiplexer pair).  Replace the "PRBS packet generator", "UDP payload inserter", and "Alignment pad inserter" with your own IP (and same thing on the receive side, if needed). If you don't need the NIOS / SGDMA, then you probably delete the multiplexer/demultiplexer as well and connect directly to the TSE MAC.

[Altera_Forum]

--- Quote Start ---  Hi, I didn't get the point: send and receive packets through the software API. which API software can be used in this case?  --- Quote End ---   It depends on what you choose to usr as a software platform. The Altera examples use the uCOS II embedded operating system with the Interniche TCP/IP stack. This has a standard bsd sockets api (https://en.wikipedia.org/wiki/bsd_socket) that you can use to send packets from the software. Other developers prefer to use LwIP or Linux. But you will never be able to generate 750Mb+ traffic with a software solution. You need to generate your packets in hardware, and the offload example indicated by ted is a good starting point.

[Altera_Forum]

Yes, you can definitely do it that way (export and manually connect the signals). But my preference is to follow the approach in the UDP offload example, and bundle your IP in Qsys components in order to avoid having to make those connections manually, and to make it easier to build a more complex system in the future. 

 And yes, you always have to recompile the project if you change something.

[Altera_Forum]

Hi,  

Every design I see in Qsys come with NIOSII Processor on the internet. Is it not possible to make a design in Qsys without a NIOSII Procesor or?   Anyway, can I get idea about how I can control the following signals in Verilog/VHDL design for streaming data?  The problem is I am not using NIOSII Processor in my design, therefore I need to write some kind of logic in Hardware to control them in order to send continuous data stream and finally integrate them in Qsys as a component.     set_10  set_1000    tse_mac_transmit.data  .endofpacket  .error  .empty  .ready  .startofpacket  .valid    tse_mac_receive.data  .valid  .endofpacket  .empty  .ready  .startofpacket  .error  I have seen some info on online training as below but this is not sufficient as logic is missing there and that is also controlled by NIOSII Processor.  // streaming sink interface (for input data)  output asi_RGBIN_ready,  input asi_RGBIN_valid,  input [31:0] asi_RGBIN_data,   // streaming source interface (for output data)  input aso_XYZOUT_ready,  output aso_XYZOUT_valid,  output [31:0] aso_XYZOUT_data,

[Altera_Forum]

--- Quote Start ---  Hi,  Every design I see in Qsys come with NIOSII Processor on the internet. Is it not possible to make a design in Qsys without a NIOSII Procesor or?    --- Quote End ---    It is definitely possible to make a Qsys design without using a NIOS II processor. The examples all include a NIOS processor because that is what most people do.    --- Quote Start ---   Anyway, can I get idea about how I can control the following signals in Verilog/VHDL design for streaming data?    --- Quote End ---   The transmit and receive ports are Avalon-ST. You send/receive an Avalon-ST packet containing the Ethernet packet. It's pretty simple. Avalon-ST is described in this document: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf  set_1000 and set_100 are described in the TSE user guide (search for their names and you will see both diagrams and written explanations). http://www.altera.com/literature/ug/ug_ethernet.pdf   As previously mentioned, you may want to consider working through the UDP Offload example and just keep deleting stuff you don't need until you are able to figure out how everything works as you will learn a lot by having done that exercise.

[Altera_Forum]

If you aren't using a CPU, you will also have to implement an avalon master to configure the TSE. IIRC after a reset both the tx and rx paths are disabled and need to be enabled through the control register. Depending on your PHY you may also have to read or write a few MDIO registers. 

It's doable, but both the initializations and part of the protocols you may have to use (ARP, DHCP....) are better handled in software, even if once initialized you only use hardware to generate or process the packets.

[Altera_Forum]

--- Quote Start ---  If you aren't using a CPU, you will also have to implement an avalon master to configure the TSE. IIRC after a reset both the tx and rx paths are disabled and need to be enabled through the control register. Depending on your PHY you may also have to read or write a few MDIO registers. It's doable, but both the initializations and part of the protocols you may have to use (ARP, DHCP....) are better handled in software,   --- Quote End ---    Does it mean you are recommending to use CPU to ease the work :)     --- Quote Start ---   even if once initialized you only use hardware to generate or process the packets.  --- Quote End ---    So, it will be somehow similar to "UDP offload example" recommended by ted. Does it fulfill speed requirement (750Mbps+), if I proceed in this way?

[Altera_Forum]

Yes I recommend to use the CPU, as they do in the offload example. It will make everything easier. IT doesn't need to be very powerful, so even the /e core, that doesn't require a license, can be used. 

As long as your hardware module is able to generate UDP packets on the avalon stream at 750Mbps, the TSE should be able to follow. Just check that the CPU configured the TSE and the PHY correctly in gigabit mode first.

[Altera_Forum]

Hi,  

If I want to give continuous data stream input from ADC (10 bit) to this "UPD Offload example", then where I have to change in this design? I mean at which component?

[Altera_Forum]

You would need to change the GEN block. This is the one generating the packet's data payload.

[Altera_Forum]

Hi, 

Is it compulsory to use External RAM (and thus DDR2 SDRAM controller) in "udp offload example"? I really don't understand the purpose of it in this project.   If so, is DDR2 SDRAM controller compatible with Quartus Web edition (Free version) and CycloneIVE or there is some kind of licence stuff?  I am asking this because following error occurs on compilation. Error (292019): Core "DDR2 High Performance Controller" (6AF7_00BF) is not enabled for current device family

[Altera_Forum]

You can use whatever RAM you like (on-chip, off-chip, SRAM, SDRAM, etc.). 

 The RAM is there so that software (by default iniche) has storage for Ethernet frames. The SGDMA controllers transfer the frames between RAM and Avalon-ST (for the TSE ports).  It sounds like you need to change the memory controller to match whatever memory you have in your hardware design.

[Altera_Forum]

Hi,  

To generate PRBS packet, LFSR5 is used for 32 bits but I didn't understand the statement    next_value <= ((((next_value << 5) & 32'hFFFFFFE0) | ((next_value >> 27) & 32'h0000001F)) + 32'h33557799);  in this program:  begin  if(go_bit & !running_bit)  begin  next_value <= initial_value;  end  else if(((state == DATA_STATE) || (state == EOP_STATE)) && aso_src0_valid && aso_src0_ready)  begin  next_value <= ((((next_value << 5) & 32'hFFFFFFE0) | ((next_value >> 27) & 32'h0000001F)) + 32'h33557799);  end  Theory seems to be clear from here  http://www1.verigy.com/cntrprod/groups/public/documents/webcontent/cnsmprod_020300.pdf  but not the program.  could anybody please explain little bit?

[Altera_Forum]

Hi, 

 As I need only point to point system (not TCP/IP or UDP), therefore I modified the Tutorial (UDP offload Example) as in attachment.  Could anybody please check, if it will be feasible?

[Altera_Forum]

Yes it will work, as long as your custom GEN module generates a correct Ethernet Header. If you don't have the header, it will be dropped by the receiving end. 

As for the line code from your previous message, it does a 5-bit rotation of the generated value on the left, and adds a constant value to the result. The(next_value << 5) & 32'hFFFFFFE0part shifts the value 5 bits on the left, and the (next_value >> 27) & 32'h0000001F)part gets the 5 most significant bits (that are dropped by the previous shift) and put them back in the 5 low bits of the new value. Those two operations combines do the rotation.

[Altera_Forum]

Hi, 

I am little bit confused about control signal of DEMUX in the design (attachment above). Because in "UDP offload example", there are 4 channels which is controlled by channel signal coming from "UDP channel mapper component" for DEMUX. But in my case (Point to point system: see attachment above), I just need to distinguish in DEMUX which signal goes to NIOSII Processor and which signal to hardware and I am confused about control signal of DEMUX.  Could anybody please explain it?

[Altera_Forum]

The "control signal of DEMUX" is the Avalon-ST "channel" signal: the DEMUX is simply routing the incoming Avalon-ST packet (your ethernet frame) to the Avalon-ST interface that is indicated by the 'channel' signal. 

 In the UDP offload example, the "UDP port to channel mapper" is the component which creates the 'channel' information, as it is not something normally part of the TSE output. In this example, it is basically a small lookup on the UDP packet 'port' and if a match is found in the control registers, it sends the packet with the corresponding channel number; otherwise it sends it to channel "4" which will end up with the NIOS software via the SGDMA. This is on or around line 513 of udp_port_to_channel_mapper.v  For getting started, I would recommend to continue to use the existing mapper component, but only connect your new component and the NIOS SGDMA ports to the DEMUX. Or, you can copy & modify the original mapper and alter it to only support (2) channels.

[Altera_Forum]

--- Quote Start ---    For getting started, I would recommend to continue to use the existing mapper component, but only connect your new component and the NIOS SGDMA ports to the DEMUX. Or, you can copy & modify the original mapper and alter it to only support (2) channels.  --- Quote End ---   Hi ted! what about the packet format which I have at this point? I have not sent "UDP packet" but just Ethernet packet without IP and UDP Encapsulation.  As far I understood in "UDP port to channel mapper" component, It also doing some operation concerning IP and UDP packet.