Port rate, required width

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Port rate, required width

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I am trying to find information about how the port rate is determined for an output. I have a output driving the clock to an DAC. During compilation i got a critical warning that the combination of I/O standard and drive strength (3.3V LVCMOS and minimum current) only supported less than 64MHz. Time Quest reported that the minimum pulse width requirement was not met (required 15.686, actual 10.000). I tried changing the drive strength to maximum and the warning went away, but Time Quest still report the same minimum pulse width violation. I am working with a EP3C80F484C8 device.

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