This kinda goes with my earlier post about generating a write-enable signal but I was wondering if anyone can share how they'd handled a similar situation in the past.
In order to get my performance up somewhat I'm registering the address/data/control signals to an external SRAM. Aside from the extra latency, I *still* need to create a solid write pulse. Since it's SRAM the data- and address hold time are 0ns, which makes it easier. The way I was going to approach the write pulse though is to logically-OR in the logic-low write-enable in with the clock AFTER the register. So latching a 1 into nWE would or that in with the clock. Not very pretty.
Some alternatives I've considered:
- Clock the registers at 2-to-4 times the actual clock speed and create a clean write-enable using a small state-machine
- Use a PLL (although that may or may not be available)
Suggestions?
-Mux
