Arria V x16 DDR3 Layout off bank 4

Programmable Devices

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Arria V x16 DDR3 Layout off bank 4

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I could use some help with an example layout off bank 4 GX/F27 (26x26 package) to the DDR3 device. Can anyone offer some assistance.

My (virtual) AF1 pin is the bottom right. DDR3 directly to the right off the AF side.

I'm good on layout guidelines, trace length limits, matching, and the like.. Just trying to save some time with BGA/DDR3 orientation and route paths. I've spent a little time with GC-Preview and the Arria V evaluation board files.. This is however x32 bus and the F35 package.. Relative pin mapping/positions are not the same.

Thanks

-D

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