hi guys, i have an available design in hdlcoder of matlab and i can generate VHDL code from it, i use hdlcoderlms demo and use codec 24 bit on de2 to AD/DA convert with sample rate is 48Khz, i download the VHDL code into board and run but nothing happen, when i just use codec interface (by VHDL ) module, i can hear desire signal from my laptop, but when i combinate with lms module (VHDL code from hdlcoderlms) so i can't hear anything at output of codec. both modules i use same clock is 27Mhz, so that the 48Khz can affect the working of LMS module or i do something wrong
