Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16612 Discussions

Executing an OpenCL host program on Cyclone V SoC

Altera_Forum
Honored Contributor II
1,036 Views

Hi all, 

 

I'm running into a problem when trying to execute my host program running on the Cyclone V SoC HPS. 

The HPS runs a Linux OS, more precisely one based on the example sd card image given in SoC EDS, 

 

Don't hesitate to ask for clarifications, I realize I'm addressing a specific problem. 

 

This is what I get : 

 

root@socfpga:~/workspace/prog# ./prog After reprogramming, FPGA is not in user mode (power up phase)! --------------------------------------------------------------- -- 1 platform(s) -- Platform 0: -- CL_PLATFORM_NAME: Altera SDK for OpenCL -- CL_PLATFORM_VENDOR: Altera Corporation -- CL_PLATFORM_VERSION: OpenCL 1.0 Altera SDK for OpenCL, Version 13.1.4 -- CL_PLATFORM_PROFILE: EMBEDDED_PROFILE -- CL_PLATFORM_EXTENSIONS: cl_khr_byte_addressable_store cles_khr_int64 cl_altera_live_object_tracking cl_altera_compiler_mode --------------------------------------------------------------- -- Found 0 device(s) (type: CL_DEVICE_TYPE_ALL) ../../ocl_utils.h: 98: in oclInit() : -30 (CL_INVALID_VALUE). ../main.c: 240: in main() : -30 (CL_INVALID_VALUE). 

 

The host finds 0 device at clGetDeviceIDs(), which causes the end of the execution. I tried to pass CL_DEVICE_TYPE_ACCELERATOR as a device type and got the same result, which lead me to think the FPGA is not detected. 

 

 

 

The warning on top of the output (which is not issued by my code, but probably by the Altera OCL Platform) seems to say something's wrong with the FPGA configuration. As a matter of fact, I didn't flash the FPGA with a .aocx file, because aocl won't do it : 

 

17:15 ~/.../workspace/implem/$ aocl flash prog_kernel.cl -------------------------------------------------------------------- No board flash routine supplied. Please consult your board manufacturer's documentation or support team for information on how to modify the default FPGA image. --------------------------------------------------------------------  

 

My environment variable is correctly set : export AOCL_BOARD_PACKAGE_ROOT=/opt/Altera/13.1/hld/board/c5soc  

 

=> Is this normal behavior for the Cyclone V SoC Dev Kit Board ? 

 

 

 

I tried programming the board with the top.sof file generated by aoc, using Quartus Programmer instead of aocl ; the warning did disappear, but the host still cannot find a device. 

 

Can any one tell me what part of the process I did wrong ? Thanks in advance :) !
0 Kudos
0 Replies
Reply