error 10170: HDL syntax error in Verilog

Altera_Forum · ‎04-18-2014

Hi, i got some trouble for the code i developed:

when i execute this code:

if(rst==1'b1)

begin

38. cs [0] = 4'b0;

39. cs [1] = 4'b0;

40. cs [2] = 4'b0;

41. cs [3] = 4'b0;

42. cs [4] = 4'b0;

43. s [5] = 4'b0;

end

then compile and i got that syntax:

Error (10170): Verilog HDL syntax error at digitalclock.v(39) near text "="; expecting ".", or an identifier

Error (10170): Verilog HDL syntax error at digitalclock.v(40) near text "="; expecting ".", or an identifier

Error (10170): Verilog HDL syntax error at digitalclock.v(41) near text "="; expecting ".", or an identifier

Error (10170): Verilog HDL syntax error at digitalclock.v(42) near text "="; expecting ".", or an identifier

Error (10170): Verilog HDL syntax error at digitalclock.v(43) near text "="; expecting ".", or an identifier

please note line 38!

please help me solved this error, thank you! :)

Altera_Forum · ‎04-18-2014

I solved that error! :)

we should declare always(posedge...) instead of always (edge...) in Verilog. :)

Altera_Forum · ‎04-22-2014

Hi,

Using 2014 version of Quartus II software (web edition), I have problem compiling the following code receiving error 10170.

module shifter16 (A, H_sel, H)
    input A;
    input H_sel;
    output H;
    reg  H;
    always @ (A or H_sel)
    begin
        if (H_sel)
            H={A,1'b0};
        else
            H={A,A};
    end
endmodule

Error received:

Error (10170): Verilog HDL syntax error at shifter16.v(2) near text "input"; expecting ";"

Any help would be appreciated.

Altera_Forum · ‎07-19-2014

it quite easy, you shoud declare "module shifter16(A,H_sel,H);" not "module shifter16 (A, H_sel, H)"

to complete a command line include module declareation, you must use ";"

:)