Error: Can't find the instance. Download a design with SRAM Object File containing t

[Altera_Forum]

when i perform sigtap ii ,the project don't have any problem before. but recently i add some module to it and use modelsim to simultate it ,then when i perform it again,it shows that  

 "Error: Can't find the instance. Download a design with SRAM Object File containing this instance." what is the problem. i can sure that the .sof file is updated correctly.    when i perform the project which duplicated it from the right operation file before , it workes well. then, i modify the width of the fir filter's output data,it fail to work.when i change the   width back to 35 ,it works well again. it seems that the width can only be set to 35,what is the problem?    finally，i find the question is the project can't change anything .if you change it ,it can't work,if you change the modification back ,sigtap works well.   please ,help me find the question.

[Altera_Forum]

Hi, 

 Can you see the SignalTap instance in the fitter report? If no; it's not in the .sof. If yes; do you use the correct stp file in SignalTap?  Regards

[Altera_Forum]

,yes ,i can see it.today, when i perform the project which duplicated it from the right operation file , it workes well. then, i modify the width of the fir filter's output data,it fail to work.when i change the width back ,it work well again.what is the problem?

[Altera_Forum]

I would use the node finder in SignalTap to make sure that the nodes that you tap are still there after the change. If you are using post-fit node names these may change when you change the width of the data path. For instance, if you made the width of the FIR output narrower, then your SignalTap instance may have references to non-existing nodes. Furthermore, I would expect a critical warning by the end of the map report related to signaltap that could shed more light on what has gone wrong. 

 Regards

[Altera_Forum]

Thank for your patient answer.the nodes are still there after change and there are no any critical warning according the report. meanwhile, i find i can download the .sof file to hardware with the programmer.

[Altera_Forum]

Hi, 

 So to summarize (as I understand it): There is no indication in the map report that the stp-file is pointing towards illegal nodes in the design. The signaltap instance is present in the fitter report. If the width of the FIR-filter is other than 35 bits the signaltap sw can't connect to the debug core.  To be honest, I'm not sure what's going wrong here... Have you tried to create a new signaltap instance from scratch with the newest version of the project?  Cheers J

[Altera_Forum]

when i change hardware and choose one with more dvanced chip , eveythiing is ok. to my surpise,the former hardware can work in certain condition,such as 35 width's FIR and can't work on others condition.what is the reason?

[Altera_Forum]

Hi, 

 It's a bit hard to speculate about that without knowing which different devices you have been using, or the nature of the design. Do you mean that the design only works when the width is 35 bits, or do you mean that it's only possible to see the SignalTap instance when the width is 35 bits? By saying that everything is OK, do you mean that the design indeed works as intended in HW?  Regards J

[Altera_Forum]

the hardware i used before is EP2C20Q240C8. and now i use ep3c16f484c6.everything is ok that means when i change the width or other something,the signaltap indeed works.however when i use EP2C20Q240C8,signaltap can't works on the condition that the fir width choose to 12.

[Altera_Forum]

Hi, 

 I'm sorry, but I can't explain that for you :(  Regards J

[Altera_Forum]

thank you all the same