have somebody using 'APFC_BOOT_ADDR' instruction to resolve the 0x20000 problem?

[Altera_Forum]

I find that if the .elf is larger than 128KB, the flash-programming operation will cover the address of the .pof file in the flash at AP configration mode, have somebody resolved this problem. 

 The org datasheet recommends the jtag instrction of 'APFC_BOOT_ADDR', but i don't know how to use it, who can help me, thanks!

[Altera_Forum]

Thank you everybody, i have get a method to complete my design for large .elf file application.  

 In fact, the .elf file can be programmed to a self-defined address offset relative to the cfi-flash at AP configuration mode, but it must modify the reset offset of the entry address of the CPU at the SOPC/QSYS options set, this offset must be the same to the .elf programming offset!  step 1: set reset offset option of the CPU in SOPC/QSYS, step 2: rebuild the quartus project, generates the .sof file, step 3: convert programming file, .sof to .pof, step 4: programming the .pof to the cfi-flash, refer to an478, step 5: open nios ii, set bsp editer options, update the bsp package, step 6: rebuild the app sofware to generate the .elf file, step 7: programming .elf and .zip file to flash, note that the .elf programming address offset must filled refer to step 1,  step 8: re-power, running ok!  Note that the offset from 0x0 to 0x20000 is 128kB for the default .elf programming space at AP mode, if this space is not enough for an applicaion, it must modify the .elf file to another address. From 0x20000 to a dedicated offset is for the .pof file, 0x20000 is the recommended start offset of the page 0, the end offset of the page 0 is defined by the FPGA model that be use, at my design, the .pof file of ep3c120 is allocated from 0x20000 to 0x38000, that i can program the .elf and rozipfs files to the space from 0x400000, this has tested successfully, At AP mode, the selected flash size is usually large enough to satisfy this method, you can try like this, good luck!