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in the latest quartus II 13.1 , when i use dual ram , how can i choose the output data is old or new when reading and writing happened at the same moment?
in the megwizard ,i can't find the proper option to choose which to be send out. and another question ,is there any way to creat a dual part ram with inital data and do not need megwizard to decide wich data to output when read and write at same time. thanksLink Copied
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For concurrent accesses to the same location the choices is 'old data' or 'random mix of old and new bits'.
If the memory type supportd OLD_DATA and you are using a single clock, then there ought to be a tick box.- Mark as New
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Hi,
I think the Options are old data, i.e. the data being overwritten from the other port is shown a the "read Access side" and new data being a feedthrough of the Input data that are to be written and the output (Output being "wired" to Input rather RAM Location.) There shouldn't be a mix of old and new bits - at least if the data and RAM ports are registered to System Clock (i.e. not asynchronous)... Otherwise the mix of data will be more due to the Input on the write side is not stable (bits are "arriving" asynchronous) at read Access... But this would be same if asynchronous data would be just registered once and by this treated as synchronized...- Mark as New
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The 'problem' is that the fpga timings don't allow for the data to propogate through the memory block - doing do would reduce Fmax significantly.
So during the clock cycle the output value from the memory changes from 'old data' to 'feed through of new data'. What the reading hardware sees depends on the propogation delays between the memory cell and the final latch. Remember also that different bits of a word are likely to come from different memory blocks - so see different propogation delays. M9K blocks definitely give random patterns when fed with two copies of the same clock and without OLD_DATA selected.
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