- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Can anyone please tell me how to increase Power Estimation Confidence level to high, the below statement is what i get in my compilation report always Power Estimation Confidence Low: user provided insufficient toggle rate data can anyone tell me how do i provide sufficient toggle rate data.Link Copied
7 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Tausen,
Thanks for the reply, i tried following your method but couldn't figure out few things like- How do you set pin placements in the pin planner
- How do you create a clock constraint in the TimeQuest Timing Analyzer
- Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
- Warning: Node: state
- Warning: Relative toggle rates could not be calculated because no clock domain could be identified for some nodes
- Create project and top-level entity (.vhd file)
- Create a testbench - it is important that the stimulus you create in the testbench represents a realistic, typical scenario!
- Go to assignments -> settings -> simulation and add a test bench, choose the file you made in the previous step and choose a design instance name you can remember such as "dut" (should match the entity name in the testbench!)
- Run compilation and RTL simulation to verify that the design and testbench works
- To make PowerPlay happy and remove some warnings, I set up pin placements and clock constraints as well:
- Assignments -> pin planner, set pin placements
- Open TimeQuest Timing Analyzer and create a clock constraint matching the clock you'll use, make sure you export an sdc file
- Under project -> add/remove files in project, add the newly created sdc file to the project
- I then set up PowerPlay to write signal activities used, write signal activities to report file, write power dissipation by block to report file. Not yet using an input file.
- Running PowerPlay now results in confidence "Low: user provided insufficient toggle rate data"
- Back to assignments -> settings, simulation and do some configuration:
- Generate VCD file script, under script settings tick "all signals"
- Design instance name: set to match entity in testbench, in my case "dut"
- Under more EDA netlist writer settings, set architecture name to match architecture in you design (in my case "rtl") and make sure "do not write top level vhdl entity" is off
- Finally, run a gate level simulation. This should generate a vcd file in the simulation/modelsim/ directory
- Now, back in assignments -> settings -> powerplay, tick "use input file(s)" and add the newly created vcd file
- Running PowerPlay now should give you a higher confidence - I'm getting "High: user provided sufficient toggle rate data" with my design now, although it might depend on a number of things that I have no idea about
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start ---
- How do you set pin placements in the pin planner
- How do you create a clock constraint in the TimeQuest Timing Analyzer
- Warning: Node: CLOCK_50 was determined to be a clock but was found without an associated clock assignment.
- Warning: Node: state
- Warning: Relative toggle rates could not be calculated because no clock domain could be identified for some nodes
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Tausen,
I did create a clock constraint of 20ns as in my project and the sdc file was already added before and tried it, but didn't have any changes, it still shows the same result. Do we need to create a SDC file always whenever we create a clock constraint, if so how do i create it. Thanks --- Quote Start --- Under assignments, choose pin planner. Then choose a location for each port in the table in the bottom, see screenshot: http://www.alteraforum.com/forum/attachment.php?attachmentid=9443&stc=1 If you can't figure this one out, just try without it - I'm not sure its even necessary. Open the TimeQuest Timing Analyzer. Click "Create timing netlist". Then go to constraints and click "Create clock" and fill out the details - in my case, name is "clk", period is 10ns, rising edge at 0ns and falling edge at 5ns. Don't forget to export the sdc file. Yes - for the "do not write top level vhdl entity"-option, I'm guessing there's something like "do not write top level verilog entity"? I think it is off by default, though, so you might not have to worry about that one option. Try again once you've created a timing constraint and added the sdc file to the project - that should help. --- Quote End ---- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Tausen,
I created a clock constraint of 20ns as in my project and the SDC file was already added from the earlier attemp, but still the result is the same. Do i need to create a new SDC file whenever i create a clock constraint, if so how do i do it?- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Tausen,
After i added the SDC file as you mentioned, i compiled my project but there two errors being generated which are Error: Text Design File must contain a Subdesign and Logic Section Error: Node instance "auto_generated" instantiates undefined entity "mult_rat" These errors even stop from running PowerPlay Analyzer tool...any suggestions Thanks- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I'm sorry, I'm not familiar with those warnings. When saving the SDC file in TimeQuest, did you save it with the extension sdc? (that is, does its name end with ".sdc"?)
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Yes Tausen i had saved it with a .sdc extention.
--- Quote Start --- I'm sorry, I'm not familiar with those warnings. When saving the SDC file in TimeQuest, did you save it with the extension sdc? (that is, does its name end with ".sdc"?) --- Quote End ---
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page