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Hello,
I want to build a Qsys design that has the following 1- 1x DDR3 RAM 2- 2x NIOS II 3- IO's for each NIOS II Each NIOS should work independent from each other (like two separate system) The DDR3 will be used as instruction and data memory for both NIOS's The question is, how can I manage the DDR3 to be connected to both NIOS's? I mean both NIOS's will share the interface to the DDR3, what would happen if both NIOS's want to use the DDR3? From the C code side, I can say Address x to y of DDR3 will be used by CPU1 and address y to z will be used by CPU2. Is this enough for managing the DDR3 usage? Thanks in advance for your inputs hbsLink Copied
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