So I have an Arria V SOC Dev Kit and am struggling with it.
I have the DIP switches set as per the kit user guide.
I am trying to run "Getting Started with Hardware Library" section of the SOC EDS User Guide
I can load the code, and the DMA setup runs OK.
The FPGA setup first fails because the MSEL switches are not set as expected (0). So I try again with them set at the four values corresponding to each of
ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC
ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC
ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC
ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC
and every time get a log of e.g.
INFO: Setup FPGA System ...
INFO: MSEL [2] configured correctly for FPGA image.
INFO: FPGA Image binary at 0x201e0e0.
INFO: FPGA Image size is 2275970 bytes.
ERROR: Setup of FPGA return non-SUCCESS -2.
That the examples and instructions don't work out of the dev kit box is very disappointing.
Can someone from Altera please help.
Thanks.
