Hi everybody,
when I start a NativeLink gate-level simulation for a Stratix-V design, modelsim (Altera Starter) complains that there is no .sdf file.
Error: (vsim-SDF-3196) Failed to find SDF file "top.sdo"
The Stratix V Device Design Guidelines (AN-625-1.1) say: "Timing simulation uses the timing netlist generated by the TimeQuest Timing Analyzer, including the delay of different device blocks and placement and routing information. You can perform timing simulation for the top-level design at the end of your design flow to ensure that your design works in the targeted device."
However, in the Quartus II Handbook notes (Vol3, 1.Simulating Altera Designs) I read: "Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is not supported for Arria V, Cyclone V, or Stratix V devices."
Does that mean that gate-level simulation is supported for Stratix-V parts or not?
I can run the simulation in modelsim without passing the "sdftyp" parameter, but is the simulation then producing reliable results?
If gate-level sim is not supported, is there another way to generate a vcd file for the PowerPlay tool?
Thanks
Heiner
