FPGA to HPS Bridge access

[Altera_Forum]

Hello everyone,  

 I've been trying to send data from FPGA to HPS. I have a few soft IP cores in the FPGA and I want the HPS to read signal data from one of these cores (2 signals of 16 bit width from the top level module). My design is based on the ghrd for Cyclone 5 SoC. These are some of my doubts, 1) In the Qsys design, how do I connect signals from my top level module to the f2h_axi_slave in the hps component?  2) Also how do I write a program (in DS-5) to read information from FPGA? Will I have to map addresses over the f2h bridge base address (similar to how it is done for h2f bridges)?  Thank you!

[Altera_Forum]

#1 you can either create a Qsys component with an Avalon-MM or AXI master interface and connect it to the H2F bridge interface that is exposed or you can click on the H2F bridge slave port and "export" it which will make it available outside of the Qsys system. Basically it's your call, I typically use the former since I'd rather design standard interfaces and let the integration tools wiring things up for me but if you prefer wiring and adapting interfaces manually that's possible too. 

 # 2 You don't need to remap the H2F bridge like the other two bridges but you do need to make sure it recieves a valid clock and is pulled out of reset.

[Altera_Forum]

Hi. Thanks for your response.  

# 1 I think exporting into the top level module would be easier.   # 2 Could you please elaborate this point? I have made sure in the Qsys design it is connected to a valid clock. But how do I read values from a particular fpga peripheral address ? Would I need to use something like alt_read_word() function from the socal.h file? If so, then I would have to map the address? For example, would this be the right way to do it?  uint32_t signal_value = alt_read_word (f2h_base_address + peripheral_address)  Thanks again!

[Altera_Forum]

Sorry for# 2, I thought you wrote F2H as a typo. F2H is for the FPGA to access the memory space of the HPS. For the HPS to access the memory space of the FPGA you have to access the H2F or lightweight H2F bridges (which need to be remapped like you said in the first post). 

 So the calculation for the physical address would be: h2f_base_address + peripheral_address.

[Altera_Forum]

Thank you so much BadOmen.  

I can successfully write to the peripherals via the bridge. However, I'm having problems reading data from those one of those peripherals. This particular PIO is defined as 'input' in Qsys and exported into the top level module where it is assigned a signal. I want to read this signal value in the HPS/DS-5. I used functions (alt_read_byte()) from the socal.h but it returns with a constant garbage value (28). I then assigned this pin the value '1' (in top level design) and was hoping I will read value '1' at the same peripheral address (in DS-5) but again saw the same '28'.  Peripherals defined as 'output' (in Qsys) works correctly when function alt_write/read are used, but not for the 'input' peripherals. Is there another way to do this? or is the function I'm using wrong?

[Altera_Forum]

I fixed the problem. While mapping in the program in C, the output peripheral address was out of range. 

 Now I have a new SYNCHRONIZATION issue. I am sending data to the FPGA and performing some computations (Using FFT Megacore to be specific) and then reading it back in HPS. I am seem to be losing data in between.  I use the FFT Megacore control signals but I still do miss data samples. Does anyone have suggestion on synchronizing the two?