stratix V Native phy Delay.

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

stratix V Native phy Delay.

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Hi all,

I am using a Stratix V native phy transceiver for my project where I have proprietary PCS block sitting next to PMA hard block of the stratix v transceiver. Now I want to calculate delay introduced in the data while transmission. I.e. TXdata->PCS->PMA->PMA->PCS->RXdata. PCS delay is know. PMA delay I am not able to find any where in the datasheet. Practically, I have found it to be 4 parallel clock cycles. Is this correct? or If any body know the theoretical PMA delay plz let me know.:)

Thanks,

Bharath

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