FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6343 Discussions

Test pattern generator from the Altera VIP suite

Altera_Forum
Honored Contributor II
889 Views

Hi, 

there seems to be a problem with the test pattern generator in conjunction with Quartus 13.1. 

When I run elaboration Quartus fails because the TPG component does not contain any ports. 

When I run the block symbol creator an empty block is created. 

The same TPG design does work with Quartus 13.0sp1. 

 

Jan
0 Kudos
0 Replies
Reply