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Hi!
In my design , a quad-channel adc 9253 is sending input to Startix 5 FPGA. In FPGA ALTDDIO_IN is used to process incoming data @ Double rate . While testing ADC alone with test patterns , I found 2nd channel of ADC output ,that is ALTDDIO_IN output is either misaligned with the frame clock of ADC or wrong patterns . adc data clock = 440 mhzadc frame clock =110 mhz
channels = 4 (lvds pairs)
input to 1 altddio_in = 2 (from channel 1) likewise , i have 4 altddio_in ...
To combat this , I have added IO constraints like this for the channel 2 . set_input_delay -add_delay -clock [get_clocks {clk_adc}] -0.5 [get_ports {i_adc_chip1_data[2]}] set_input_delay -add_delay -clock [get_clocks {clk_adc}] -0.5 [get_ports {i_adc_chip1_data[2](n)}] i found a doc from altera , that while io constraints ,virtual clocks should also be used to add input or output delay . Is the above delay setting is sufficient or wrong ???? regards JAYV
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