Altmemphy dq slack violation

[Altera_Forum]

Hello, all. Device is Arria II GX: EP2AGX45DF29I3, memory is Micron MT41J64M16LA-15E. 

 Im having a timing failure with my memory interface to DDR3. I have zero clue how to fix it at this point. This is a memory data pin (there's more instances of this failure on the same bus) that has a slack problem. I don't know how to fix a problem though the I/O.   Report Timing: Found 1 setup paths (1 violated). Worst case slack is -0.123  Here's more details:  From Node: mem2_dq[12] To Node: Video_Memory:Inst_Video_Memory_2|ddr3_controller:Inst_DDR3_Controller|ddr3_controller_controller_phy:ddr3_controller_controller_phy_inst|ddr3_controller_phy:ddr3_controller_phy_inst|ddr3_controller_phy_alt_mem_phy:ddr3_controller_phy_alt_mem_phy_inst|ddr3_controller_phy_alt_mem_phy_dp_io:dpio|ddr3_controller_phy_alt_mem_phy_dq_dqs:dqs_group[1].dq_dqs|wire_bidir_dq_4_ddio_in_inst_regouthi  Launch Clock: Inst_Video_Memory_2|Inst_DDR3_Controller|ddr3_controller_controller_phy_inst|ddr3_controller_phy_inst|ddr3_controller_phy_ddr_dqsin_mem2_dqs[1] Latch Clock: Inst_Video_Memory_2|Inst_DDR3_Controller|ddr3_controller_controller_phy_inst|ddr3_controller_phy_inst|ddr3_controller_phy_ddr_dqsin_mem2_dqs[1] (INVERTED)  Max Delay Exception: -0.036 Data Arrival Time: 2.350 Data Required Time: 2.227 Slack: -0.123 (VIOLATED)   IT looks on the technology viewer like the overall path is from the pad, through the IO_BUF, through DDIO_IN and finally to fabric. But how to I make timing on this? Can I alter a .tcl file? Is there somethign I can do in the assignment editor to that pin/port that will make it run faster? Here are my assignements to mem2_dq[12] in the assingment editor:   FROM: TO: ASSIGNMENT NAME: VALUE: ENABLED: ENTITY: <blank> mem2_dq[12] Location PIN_AG4 Yes grt_hssam_top <blank> mem2_dq[12] I/O Standard SSTL-15 Class I Yes grt_hssam_top <blank> mem2_dq[12] Output Termination Series 50 Ohm without Calibration Yes grt_hssam_top <blank> mem2_dq[12] Output Enable Group 1985 (made this up abitrarily) Yes grt_hssam_top <blank> mem2_dq[12] Fast Output Register Off Yes grt_hssam_top <blank> mem2_dq[12] Enable fine delay resolution on T11 Delay (DQS post-amble delay) On Yes grt_hssam_top  Any help is appreciated. This is occurring on dq[15] down to dq[8]. The remaining 8 are meeting timing