Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Quartus generation of netlists

Altera_Forum
Honored Contributor II
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Hello everybody, 

I am investigating the gate level simulation processes in quartus. Since I am more a CLI guy, I tried the quartus_eda command line tool. I have also read a little bit the handbook (like the "Typical Design Flow" figure 2-2 for v14.0) and a fundamental detail escapes me: 

 

Apparently you can only generate a netlist after the fitting phase, am I right ? Which means that you can't generate just a synthesis netlist (ie. after quartus_map). 

 

If so, could anyone explain me why we can't generate a synthesis netlist ? (it can save time for investigations) 

thanks
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