- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello everybody,
I am investigating the gate level simulation processes in quartus. Since I am more a CLI guy, I tried the quartus_eda command line tool. I have also read a little bit the handbook (like the "Typical Design Flow" figure 2-2 for v14.0) and a fundamental detail escapes me: Apparently you can only generate a netlist after the fitting phase, am I right ? Which means that you can't generate just a synthesis netlist (ie. after quartus_map). If so, could anyone explain me why we can't generate a synthesis netlist ? (it can save time for investigations) thanksLink Copied
0 Replies
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page