Qsys problem with auto-inserted adapters

[Altera_Forum]

Hi,  

 I have a problem with Qsys. It generates "avalon-st adapters" between my VIP functions and because of them, my design doesn't work anymore. I explain me.   I have a simple design of a TPG (test pattern generator) and an ITC (clocked video output). It works perfectly, I saw the color bars on my screen (VEEK kit). I re-generate my design and it doesn't work anymore. I compare all of my files, before and after and the only différences was in the .qip generate by Qsys. In the "wrong" file there are in addition "Avalon-st adapter" and "avalon-st adapter timing adapter". I search in the litterature and I found this document : http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf  I saw in it : "note: The auto-inserted adapters feature does not work for video IP core connections." and a command tu put in the quartus.ini to disable this function. I did it and it works perfectly again. The problem is that I have to put a frame buffer between the TPG and the ITC to go on the rest of my design and tere is not enough space internally for it so I put it on the DDR3 of the board but, Inside the DDR3 controller there is a necessary timing adaptation (see errors at the end) So I can't let my command to deactivate the auto-inserted adapters but my design don't work without it.  Is there a way to fix this ??  P.S : I work on the VEEK kit with the Cyclone V SOC board and Quartus 13.1 64bits  errors in DDR3 :  Error: mem_if_ddr3_emif_0.dmaster.timing_adt.out/fifo.in: The source has a ready latency of 0, while the sink has 1. Please insert appropriate adapter. Error: mem_if_ddr3_emif_0.dmaster.fifo.out/b2p.in_bytes_stream: The source has a ready latency of 1, while the sink has 0. Please insert appropriate adapter.