General questions from a first time user...

[Altera_Forum]

Hello all, 

I have recently discovered FPGA's thanks to Grant Searle's web site, which contains instructions on how to program a Z80 computer on an Altera EP2C5T144C8N mini board. Essentially, I've been "bitten by the bug" and want to learn and do a lot more with Altera FPGA's. So, I got an Altera DE1 board, and will start going through the tutorials and learning more about FPGA's. I do have a background in electronics and programming, so I am somewhat at ease with the structure of Quartus II software.  So, a general question: I tried to (unsuccessfully) take Grant Searle's project and import it into the DE1. Though I don't know much about FPGA's at this point (I'm learning as I go), I guess the "failure" comes from properly configuring the DE1 for memory (and also the VGA and PS/2 port) like Grant does for the EP2C5T144C8N mini board. Generally speaking, what would I have to do to get Grant Searle's file to work on the Altera DE1 board?  Thank you in advance for the replies, and helping a newcomer discover a whole new world!  Cheers!

[Altera_Forum]

Well, for a start, with a different board the pinout is going to be different, and the available peripherals may be different.  

First of all, you need to check the specs of both boards, and see what peripherals the project is using. If you have a like for like match, then you just need to change the pinout and away you go. But if they are different, then you may have to do some major project overhaul as they may have different specs, so the controllers will need re-writing.  It might just be easier to start your own project from scratch, especially as a beginner.

[Altera_Forum]

I understand it then, that there's a bit more to just compiling the software for the other board. It seems like I would not only have to compile the software, but also look through the pin assignments. I guess I would also have to specify where the software is to find the ram and VGA port, and opposed to where the software was written to find the peripherals. I should mention that I was able to successfully go through Grant Searle's Multicomp project and build the project with external ram, VGA and ps/2 ports on the mini board. I was hoping this might be somewhat of a straight forward process, but it looks like I may need to take a few steps back, get a few tutorials under my belt, and then try to understand how to port a project. Thank you for the reply.

[Altera_Forum]

If you are talking about compiling VHDL/Verilog, this is NOT software. This is hardware description language. It builds firmware for the fpga. Software is what you might run on your Z80 that exists inside an FPGA.

[Altera_Forum]

I wrote a simple top-level design for the DE1 and posted it in this thread: 

 http://www.alteraforum.com/forum/showthread.php?t=35687  Download de1_basic.zip, unzip it, (delete the qwork folder), and follow the instructions in the readme.txt file.  This does not include the use of memory or VGA, but it does provide you with a (somewhat) "Golden" top-level reference design. Its "somewhat" in that I do not have this board, so have not tested this design, but others on the forum have :)  Cheers, Dave

[Altera_Forum]

Hi Dave, 

Thank you for the small tutorial. I had a few problems getting it going, being that I have learned to run before I can walk, but persistence paid off, and I was able to generate the qwork directory. I loaded the de1.sof file, and had a look through the de1.vhd file. I don't know if I missed a small step, but I am unable to see a top level design. I am using Quartus II 64-bit, windows 7, version 13.0.1 Web Edition.  Other than that, I was able to see the green LEDs count up in binary ( Very cool!!! Makes me miss the 8-bit days =] ) and also the switches could cycle the red LEDs. I also observed the hexadecimal display counting as well. How do I view / generate a top level design? I did compile the design, but ended up with a few error messages:  Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis  Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition  Info: Processing started: Sat Jul 12 20:59:20 2014 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off de1 -c de1 Warning (20028): Parallel compilation is not licensed and has been disabled Warning (12019): Can't analyze file -- file ../../../../../../../../../dwh/DE1/de1_basic/src/hex_display.vhd is missing Warning (12019): Can't analyze file -- file ../../../../../../../../../dwh/DE1/de1_basic/src/de1.vhd is missing Error (12007): Top-level design entity "de1" is undefined Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 3 warnings  Error: Peak virtual memory: 430 megabytes  Error: Processing ended: Sat Jul 12 20:59:21 2014  Error: Elapsed time: 00:00:01  Error: Total CPU time (on all processors): 00:00:01   On a good note, I seem to have gotten a step closer to porting Grant Searle's Multicomp to the DE-1, and get it to boot to a blink cursor with a blinking "d". That tells me video ROM isn't set up properly. I was able to assign pins to the SRAM, but have not figured out how to "route" the video the SDRAM, and have not figured out how to port the ROM "outside" of the FPGA and onto the FLASH. I "think" I can simply copy the BASIC.HEX into the flash, but I don't know how to "connect" the flash to the FPGA in the "program" ( Sorry if I use the wrong terms here... still learning quite a bit... =] ).  Thanks again for everyone's help!!! I truly appreciate it!!! =]

[Altera_Forum]

Hi, 

  --- Quote Start ---   Thank you for the small tutorial. I had a few problems getting it going, being that I have learned to run before I can walk, but persistence paid off, and I was able to generate the qwork directory.   --- Quote End ---   It sounds like you did not read the readme.txt file included with the example. I have updated the zip file and removed the qwork folder (to avoid the confusion it caused).   Please follow the readme.txt instructions (repeated here):  Terasic DE1 'basic' example --------------------------- 4/25/2012 D. W. Hawkins (dwh@ovro.caltech.edu) Terasic DE1 Cyclone II FPGA kit 'basic' design. Counters are used to blink or generate counts using the three onboard clock sources as follows; * KEY is used as the reset input * KEY drive the 3 MSBs of the red LEDs * 7 switches connected to 7 of the 10 red LEDs. * 8 green LEDs blinked using the 24MHz clock * Hexadecimal displays A and B count based on the 27MHz clock * Hexadecimal displays C and D count based on the 50MHz clock The design can be synthesized as follows; 1. Unzip the example design into c:/temp/de1_basic when using windows to unzip the file, unzip de1_basic.zip into c:/temp and the folder c:/temp/de1_basic will be created. 2. Start Quartus II. 3. Click in the Tcl console. If the Tcl console is not visible, bring it up using View->Utility Windows->Tcl console 4. Use the Tcl console to change to the directory to the de1_basic/ folder, eg., at the Tcl console type tcl> cd {c:\temp\de1_basic} Where 'tcl>' is the console prompt. The parathases {} pass the Windows format directory to Tcl as a list variable. This allows you to copy and paste the directory path from Windows Explorer. 5. Run (source) the synthesis script tcl> source scripts/synth.tcl The Tcl console will then output the build sequence: Synthesizing the DE1 'basic' design ----------------------------------- - Quartus Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version - Creating the Quartus work directory * C:/Temp/de1_basic/qwork - Create the project 'de1' * create a new de1 project - Creating the VHDL files list - Applying constraints - Processing the design - Processing completed 6. Download the design Plug in the DE1 USB-Blaster and download the .sof file. The LEDs and hex displays should start to blink/count. Read the comments in src/de1.vhd for details on the basic design. Enjoy! Cheers, Dave 7/12/2014: Checked synthesis with Quartus 13.0sp1. Updated the readme.txt. No code changes.    Cheers, Dave

[Altera_Forum]

On to your other questions ... 

  --- Quote Start ---   I seem to have gotten a step closer to porting Grant Searle's Multicomp to the DE-1, and get it to boot to a blink cursor with a blinking "d". That tells me video ROM isn't set up properly.   --- Quote End ---   Ok. I hope you checked all of your FPGA pin assignments before you downloaded your custom design, as you can damage the FPGA I/O pins if you get the assignments wrong!    --- Quote Start ---   I was able to assign pins to the SRAM, but have not figured out how to "route" the video the SDRAM, and have not figured out how to port the ROM "outside" of the FPGA and onto the FLASH. I "think" I can simply copy the BASIC.HEX into the flash, but I don't know how to "connect" the flash to the FPGA in the "program" ( Sorry if I use the wrong terms here... still learning quite a bit... =] ).  --- Quote End ---    These comments are a concern. If you look at the file src/de1.vhd, the top-level entity has port names that correspond to *EVERY* connection (pin) on the DE1 board, and scripts/constraints.tcl applies the appropriate pin assignments.  If you use the DE1-basic design as a template (i.e., copy-and-paste the folder as the starting point for a new design), and create your custom logic inside de1.vhd, and run your own edited/modified version of the synthesis script, then you do not need to worry about pin assignments, as they are already done for you.  If you want to work with a schematic top-level design, you can do that, you just need to use the same port names as used in the top-level de1.vhd file, and the constraints.tcl script can be reused without changing anything.  I realize this is all new to you, so please feel free to ask questions, regardless of how trivial you think they are, and you'll get answers from forum members.  Cheers, Dave