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I have a Cyclone V and I am connecting a DMA read master to an On Chip RAM and the write master to the DDR Controller.
It seems like I am getting 600MB/sec throughput, which looks too much! Is it possible or is there something wrong? How can I calc the max throughput? The system is running at 100Mhz and my data width is 64 bits. Theorically I could achieve (64*100.000.000)/8) 800MB/sec. So 600MB/sec looks possible. Is this right? I am comparing the onchip data with the ddr data and it matches but it looks to good to be true... CheersLink Copied
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First time I've seen someone ask if they're getting too much throughput. :)
The fact that you're checking it on-chip seems promising. The controller does a lot of things to help efficiency. The high-level stuff in the handbook includes: Command and Data Reordering Bank Management Streaming Reads and Writes Bank Interleaving Predictive Bank Management Build-in Burst Adaptor etc. Efficiency is always dependent on the reads and writes, but a lot of this smooths out the low corner-cases for much better efficiency.
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