Questions of max10 on chip adc and flash

Altera_Forum · ‎03-19-2015

Hi, I am new to altera, and I am going to change my fpga from Spartan 6 to max 10, I have read several handbooks of max10, and I have several questions:

1. the max10 on chip adc

my design has strict requirement to the adc sample time point, when the max10 on chip adc sample the input after I start it? One cycle?

I plug in the adc in quartus and do the follows to start convertion.

adc_sequencer_csr_address <= 1'b0;

adc_sequencer_csr_read <= 1'b0;

adc_sequencer_csr_write <= 1'b1;

adc_sequencer_csr_writedata <= 32'b1;

2.the max10 on chip flash

How to read or write UFM in nios? Is there any reference design?

thanks!

qd0090

Altera_Forum · ‎06-17-2015

Hi,

Not sure if you are aware that Altera has publish a reference design to access the MAX 10 CFM and UFM usifn the Altera On chip flash IP via Nios.

You can refer to this AN741:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an741.pdf