Cyclone II max current

[Altera_Forum]

I am working on an alarm clock for my semester project. I have 88 leds that i want to drive with the FPGA. I am using the DE1 development board for testing the code. My plan is to switch to the EP2C20Q240 and a custom circuit board quad flat pack instead of FPGA. I have read through the data sheets that i can find. I see that each of the IO pins can source 24ma but I cannot find the total max current for the whole chip. Either i have overlooked it or it is just not there.  

 At 20ma max per LED that is a 1.76 Amps total if all of the leds are on at the same time. I assume that the FPGA would not be happy with this. I can drive each of the leds with a mosfet if the current capacity of the FPGA is a problem but with the added cost i would rather not if i do not have to.   Also, i cannot locate a reference schematic for this chip, does any one have one? i have the schematic for the DE1 board, i assume it is close enough to answer my power pin questions and how to connect the jtag port so i can program the chip (which i assume will work with the active serial programming)  any tips, advice, or input would be greatly appreciated. I am new to FPGAs but have a a lot of other electronics experience.   -scott-

[Altera_Forum]

You could use an led driver IC. There are plenty of them out there which take a serial input with an internal shift register, and they usually have a serial out for daisy chaining. You can then have just one set resistor per ic to set the led current. Here's an example from ti, TLC5925IDBQR 

You can also find some fancy ones that support blinking and dimming.

[Altera_Forum]

Read the 'DC Guidelines' in on page 10-32 of the cyclone ii device handbook (http://www.altera.co.uk/literature/hb/cyc2/cyc2_cii51010.pdf). This discusses the maximum current per group of pins, depending in the side of the device they reside on. 

 However, I recommend you steer clear of running the FPGA continuously at these currents. Whilst, on paper, the Cyclone II device may be up to what you're considering (I've not done the numbers for your requirements), they're not really intended to drive large banks of LEDs.  The LED driver route, as suggested by cronus10, is the way to solve this. Or, if you really don't like the idea controlling such a multi-channel LED driver, you could use a suitable constant current source, such as Infineon's bcr401r (http://www.infineon.com/dgdl/bcr401r.pdf?folderid=db3a30431400ef68011407a9cfc70181&fileid=db3a30431400ef68011407ab7ea10185). This will be simpler for the FPGA but vastly more complex for your additional PCB as you will need one of these LED drivers per LED.  Use the FPGA for what it's good at - as the brains of your solution - not for driving the LEDs themselves.  Cheers, Alex

[Altera_Forum]

I like the TLC5925 idea. Thank you. Is there any reference designs for it? I did not see anything in the data sheet. How would I control which led was on/off? I do not have any experience with that type of chip or communication. I don't necessarily need the answer (although it would be appreciated) any clues or direction would be helpful. I tried googling for a reference design but all i could find was an arduino project. I assume that controlling the TLC5925 would be done through VHDL?  

 -scott-

[Altera_Forum]

So i have never actually used a shift register before, which is what it looks like the TLC5925 is or has inside. From what i can tell from researching it, there is a clock pin that i connect to some clock source, and then there is a serial pin that i send the data too. Serial data is being read on each positive edge of the clock.  

 As for controlling each of the LEDs though, and please correct me if im wrong: this chip has 16 outputs, do i send a 16 bit stream of data to control which led is on? ie. if i want the first and second led (OUT0 and OUT1) to be turned on i would set the LE pin high then send a bit stream of 00000000000011? which bit should be sent first (order of the bit stream)  If this is correct then what about daisy chaining 2 chips? I assume i connect the serial out from chip 1 to the serial in of chip 2 connect both clock pins together and then do i also connect the LE pins together as well? then to light up the requested leds to i then send a 32 bit stream?  For this application what if i did this for 4 of the TLC5925 chips: connect all the clock pins together with the same clock source, connect all of the serial data in pins together to the serial out pin on the FPGA, then connect each of the LE pins to their own pin on the FPGA, this was i can set the leds in groups once a group is set i do not have to keep resetting all 64 bits it every second (this is for a 60 second progress bar with 60 leds) then when the clock hits 60 seconds i can set all 4 LE pins high and send 16 zeros on the serial line to turn off all 60 of the LEDs.   does this sound like it would work? any feed back would be greatly appreciated.  -scott-

[Altera_Forum]

It's up to you how you connect these devices up - as a chain or independently to the FPGA (you're sure to have enough FPGA I/O). 

 If connected as a chain then the first bit you send in to the first device will be the on/off state of the last channel of the last device in the chain. You'll then clock in one bit for every subsequent LED channel in the chain.   --- Quote Start ---  there is a clock pin that i connect to some clock source  --- Quote End ---   Yes, there is a clock pin but I recommend you connect this to an ordinary FPGA I/O pin. Yes the device will operate with a 30MHz clock, but that's over the top for your application. I recommend you generate the clock driving the TLC5925 from logic. By using a much slower clock generated in this way you'll have complete control of the timing into the LED drive.  Yes the LE pin should be driven to all daisy chained devices together, indicating to all devices the newly sent data should be transferred to the output drivers.  I don't see any reason why you're last suggestion won't work either (common clock & data across all devices with separate LE control). However, with the I/O you'll have available from the FPGA I really wouldn't bother. The signal integrity to each device will be far better if they are driven separately. If you do want to do this then I recommend driving separate clocks to each device. Reflections that result from a point to multi point net topology might cause functional problems on your hardware. The clock is the critical signal on this device, make sure it's integrity is good.  Cheers, Alex