[beginner] D Latch issue

Altera_Forum · ‎09-21-2014

Hi I am new to VHDL programming and I seem to have an issue simulating a D Latch in Quartus II. The main issue is that my code seems to keep transferring input D to output Q when enable E is low(0), even though I do not specify it to do so.

Here is my code:

library ieee;use ieee.std_logic_1164.all;
entity lab1 is
port(
    signal e:    in    std_logic;
    signal d:    in    std_logic_vector(3 downto 0);
    signal q:    out std_logic_vector(3 downto 0));
end lab1;
architecture arc of lab1 is
begin
    process(e, d)
    begin
        if (e = '1') then
        q <= d;
    end if;
    
    
    end process;
end arc;

Here is a link to a screencap of my vwf file. It compiles with no errors, but this is the waveform I get, and the output is wrong. (See D transfers to Q on enable 0, which is undesired)

http://imgur.com/ydhjqyv

Altera_Forum · ‎09-25-2014

Are you sure you want to build a transparant latch? it will be prone to timing issues, which you are probably seeing in the waveform (as the quartus simulator only simulates gate level designs). FPGAs are designed for clocked flip-flops.

Have you got a testbench for this code? have you tried modelsim instead?