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Two questions:
1.How do I connect multiple functions with MegaWizard together as in signals from one block to another? And how do I compile them together as one / how do I integrate multiple functions together in one project? 2.I'd like to use the ALTPLL with dynamic configuration. Are there any tutorials on how to implement such system? Like the code that is available for this function, the way it needs to be written, where to put it in Quartus, etc, for beginners? Thank you very much people :) (Quartus II v13.1 Cyclone III)Link Copied
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You need to provide readers of this forum with a little more detail, i.e., your background and knowledge and what you want to do.
Your questions imply that you do not understand how HDL languages work, so first you have to; 1. Learn an HDL language, eg., VHDL or Verilog. 2. Get something basic working, eg., blink an LED using an on-board oscillator 3. Modify the design in (2) to use an ALTPLL statically configured 4. "Improve" the design to dynamically configure the ALTPLL All of these stages could be implemented in the Modelsim simulator, and then tested in hardware using a low-cost development kit such as the Terasic DE0-nano or the Arrow BeMicro-CV board. FPGAs are somewhat daunting to start with. Forum members will help provide encouragement :) Cheers, Dave- Mark as New
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Hi Dave,
Well, actually I have some experience with VHDL and have already done some testing and experimenting with a BeMicro kit. The thing is that Quartus is more complicated than the language itself. Also I'm learning by my self so there is no body I can ask other than on this forum. Most of the time I manage to find my way through the difficulties but some times I get stuck like in this case. I managed to get a ALTPLL working but I want to make it configurable and here is where I need help. I also experimented with other cores and now would like to connect them together. So I'd appreciate if some one can show me the path. Thanks- Mark as New
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If you knew VHDL, then you know how to instantiate components and do the interconnect - you just connect them with signals.
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--- Quote Start --- Well, actually I have some experience with VHDL and have already done some testing and experimenting with a BeMicro kit. --- Quote End --- Great! Which BeMicro kit? There are three; BeMicro (with a red PCB ), BeMicro-SDK, and BeMicro-CV. --- Quote Start --- The thing is that Quartus is more complicated than the language itself. --- Quote End --- Sure, this goes for all complicated tools :) --- Quote Start --- Also I'm learning by my self so there is no body I can ask other than on this forum. --- Quote End --- You're welcome to ask questions here. I was just trying to understand what you had figured out so far. --- Quote Start --- Most of the time I manage to find my way through the difficulties but some times I get stuck like in this case. I managed to get a ALTPLL working but I want to make it configurable and here is where I need help. --- Quote End --- There is an ALTPLL_RECONFIG core, have you tried using it? The main thing you need to understand, is that you should be using Modelsim to start with, and only once you have a testbench working well, then test in hardware. So, task# 1 for you is to instantiate an ALTPLL_RECONFIG component in a testbench, and then write stimulus to access its serial reconfiguration interface. I think there is an example that comes with the MegaCore user manual ... yep, there are several ... http://www.altera.com/literature/lit-ug.jsp Try those examples, and if you get stuck, ask questions. Cheers, Dave
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Thanks Dave, you gave me the boost I needed. I'm using the red BeMicro.
I found this pdf, http://www.altera.co.uk/literature/tt/tt_my_first_fpga.pdf . I followed the instructions and managed to connect some cores together. Felt great :). I haven't tried ALTPLL_RECONFIG core as the ALTPLL has an option to add extra configuration pins to the same core and that's where I got stuck. But I'll take a look at the link you posted. I'm sure I'll find the necessary information. I only used Modelsim once but I'll practice with it too. Thanks for all the help so far. I'll keep you posted.- Mark as New
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--- Quote Start --- Thanks Dave, you gave me the boost I needed. --- Quote End --- Great! Sometimes you just need a little encouragement :) --- Quote Start --- I'm using the red BeMicro. --- Quote End --- Ok, I have this board. Its USB-Blaster JTAG interface is non-standard, and sometimes troublesome. --- Quote Start --- I found this pdf, http://www.altera.co.uk/literature/tt/tt_my_first_fpga.pdf . I followed the instructions and managed to connect some cores together. Felt great :). --- Quote End --- Excellent. In VHDL, you can put component definitions in packages and then "use" the package, or you can define a component locally. --- Quote Start --- I haven't tried ALTPLL_RECONFIG core as the ALTPLL has an option to add extra configuration pins to the same core and that's where I got stuck. But I'll take a look at the link you posted. I'm sure I'll find the necessary information. I only used Modelsim once but I'll practice with it too. Thanks for all the help so far. I'll keep you posted. --- Quote End --- This thread has a basic Modelsim simulation example http://www.alteraforum.com/forum/showthread.php?t=45770 Cheers, Dave
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--- Quote Start --- Excellent. In VHDL, you can put component definitions in packages and then "use" the package, or you can define a component locally. --- Quote End --- Or instantiate directly from the library, meaning any errors are spotted at the compile stage, not the mapping stage (in larger designs, this can save 10+ minutes).
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Hi guys, Thanks for the input. I'm reading the PLL and RECON core datasheets. Can any one please give me some basic explanation on the .mif file please? And in which way can the RECON core be reconfigured on the go? Is it by rewriting to this .mif file or there is a simpler way? Thanks.
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--- Quote Start --- Can any one please give me some basic explanation on the .mif file please? And in which way can the RECON core be reconfigured on the go? Is it by rewriting to this .mif file or there is a simpler way? Thanks. --- Quote End --- A MIF file is a blob of data, much like an Intel .hex file. Altera use it in several of their IP cores often as a way to configure IP with the correct combination of parameters, eg., consider the PLL core, which contains lots of different registers, one way Altera can avoid end-users incorrectly programming the IP block is to have Quartus generate a .mif file with consistent parameters, and then have the user load the .mif file to reconfigure the core. I'm not sure if that is exactly how the .mif file is used in this case, but you get the general idea ... Cheers, Dave
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I get it, I get it. Thanks Dave. I have downloaded any example of a Cyclone III with PLL, RECON, RAM and state machine. Very interesting example with loads of information. Also took a look at the .mif file provided and its pretty easy to understand the structure. It's the bits per registers that I need to sort of decipher now. I'm sure there is some information some where. Just have to look harder. I'm following this http://www.altera.co.uk/literature/an/an507.pdf but the PLL scan chain bitmap lacks information.
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I think I found the information in the Cyclone III device handbook. :)
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