clock definition

[Altera_Forum]

I know this is probably going to be a stupid question. I have just started using quartus and doing HDL so please bare with me. 

I was just wondering how the software knows what the clock line is in order to define a default constraint of 1Ghz to it. I can see if the model is a behavioral model perhaps it could be inferred from the structure of the lang, but let's say I do a gate level design then what?    Thank you all for your time.

[Altera_Forum]

From your code it infers a load of registers, and from that its quite easy to infer which signal is the clock. 

The 1GHz default constraint is unrealistic, and just put there to see what the real FMax is. The best you can get in the newest devices is about 400+ MHz with serious design considerations.

[Altera_Forum]

Create an .sdc file. Put in the following: 

 create_clock -period 10.0 -name clock [get_ports {clock}] derive_pll_clocks  Change the clock to whatever the name of your top-level port that a clock comes in on. The -name can be whatever you want. Make the -period value correct. Add as many create_clock constraints as necessary.

[Altera_Forum]

Thank you a priori for your kind replies. 

As I stated, I am quite new to all this. I am quite familiar with CS as well electronics (digital and analog) I just am new to all this EDA. I am teaching myself Verilog and VHDL currently. I tried The Xilinix ISE and like quartus better. But more to the point. I understand your point about clock constraints. I think more to what I was asking is if you donot define a clock constraint and run full compile the software will still define a clock of default 1 Ghz (i understand this is for testing only) and attach it to a pin (the clock pin). Does it look for a pin named clk or clock to know where to attach it or as stated by previous responder is able to tell by structure of behavioral code and registers load if doing gate level modeling?  thank you all again for helping me.  Oh by the way. I find the quartus handbook (which I have read as well was taken a few quartus online courses) quite convoluted. Any better source to learn?  thank you.             --- Quote Start ---  Create an .sdc file. Put in the following:  create_clock -period 10.0 -name clock [get_ports {clock}] derive_pll_clocks  Change the clock to whatever the name of your top-level port that a clock comes in on. The -name can be whatever you want. Make the -period value correct. Add as many create_clock constraints as necessary.  --- Quote End ---  

[Altera_Forum]

For timing, I might recommend: 

http://www.alterawiki.com/wiki/timequest_user_guide (I'm biased because I wrote it).   If a design has no .sdc, TimeQuest goes in adds high-speed clock constraints. This is called "benchmark" mode for the user who creates a quick project with some test HDL to see how fast it runs and they don't bother with an .sdc. Without a constraint it used to not optimize for timing and Altera would look bad in these benchmarks. As soon as the user starts creating clock constraints in an .sdc, TimeQuest assumes you know what you're doing and will no longer constrain stuff that doesn't have a constraint. You can always run the Report Unconstrained Paths and it will show you all the locations that drive clocks that don't have a constraint. In essence, TimeQuest knows what drives the clock ports of registers. In benchmark mode it tries to constrain them with something that was impossible(may be possible in Stratix 10), and in normal mode where a user has constraints, Report Unconstrained Paths can help.

[Altera_Forum]

Thank you for all your answers. 

Perhaps I should start another thread for this question but I thought I'd just ask it real quick. In one of my designs I'm getting a limit to fmax due to "maximum I/O toggle speed" I researched this item and I know it's a logic opinion which is set via the assignment editor. The problem is when I look in the assignment editor nothing is set, any ideas? Is it a technology setting which I cannot unset from the chip datasheet specs?    ps....I already have the timequest users guide....great work thank you for writing it.  drforbin