Optimized MOD function?

[Altera_Forum]

Hi - I know I can use a divider to do a MOD function, but the latency of the dividers I'm familiar with is 1b/tick, and I'd like something faster. Has anyone written any optimized RTL for doing a MOD function? Thanks /j (Verilog or VHDL is fine).

[Altera_Forum]

The divider core is probably as optimised as you'll get. 

Why do you need "faster"? Just set the divider core pipeline to less clocks.

[Altera_Forum]

I'm interested in latency, not throughput. As it turns out, you can do a parallel Mod function (order log(n) rather than order n) with some clever comparison logic. 

best /j