Read-only on Pin Planner

[Altera_Forum]

Hi, I am using Qsys and QuartusII (14.0) to find out which pins to use for a DDR3 on an ArriaV GZ. I am basically a hardware designer, and I have reserved all of Bank 7 for the DDR3 interface. There are plenty of pins free. 

I have used Qsys to add the Uniphy IP for the DDR3, and the synthesis works OK. Then I run the tcl script for pin assignments and run the fitter. which gives a warning that there are no exact pin location assignments for the 52 DDR pins (not a problem since I want to assign them manually). At the end of this I open Pin Planner and find that the pin assignments have been randomly allocated all over the FPGA. Again, that would be OK but every last one of them seems to be set to 'read-only'.  The answer is probably staring me in the face but since I don't use the Quartus tools very often (being a humble pcb designer) I can't see it. Thanks for any help you can offer.

[Altera_Forum]

and if you use the pin planner to delete the assignments and do them yourself, without the tlc script? Or else create a .csv file with the assignments, if you have to change the pin assignments often. 

 [edit] Just to be sure, the pins you want to use are bidirectional? [/edit]

[Altera_Forum]

could you post the csv file?

[Altera_Forum]

OK I didn't realise you have to remove the top few lines of comments. I did that and the assignments were imported without giving errors. However when I recompile the project the new .pin file is exactly the same as the old one (ie uses bank 3 and 4 instead of bank 7) so it completely ignored my .csv file.