Arria V GZ PCIe build

[Altera_Forum]

Hi I am trying to confirm the pinout of my Arria5 GZ PCIe interface by building a system with QuartusII (version 14) and Qsys. The datasheet for the Arria V GZ Hard IP for PCI express points to this link: http://www.altera.com/literature/ug/ug_a5gz_pcie_avst.pdf. Figure 2-2 on page 2-3 shows the Qsys arrangement for the core. However one of the biggest components of the system (DUT) does not support Arria V GZ. The .qsys file was not in the folder specified in the datasheet and when I did find it and opened it in Qsys I got 6 errors. Is there a better document I can use to guide me through the process and get a pinout I can use for my hardware design? Surely it can't be this difficult?

[Altera_Forum]

Couple thoughts? Did you try the Stratix V example design in Qsys? take a look at the 14.0/ip/altera/altera_pcie/altera_pcie_hip_256_avmm/example_design/sv. Arria 5 GZ is very similar to SV so if you can successful compile the SV design in Qsys, you should be able to modify that project over to Arria V GZ. I just compiled that qsys file in a new project with Stratix V in 14.0 and it worked fine. I don't have Arria 5 GZ installed so I didn't complete the last few steps. I know, the docs aren't very clear but the new DMA ref design in 14.0 is now in the IP folder, under example designs.