Avalon MM Master Template - Writing makes Nios2 crash

Altera_Forum · ‎09-29-2014

Hi,

I've implemented a Avalon Master MM master template to manually write a SDRAM (which is shared with my Nios processor). The source code is the following:


-- From component
writer_control_fixed_location  => '0',  -- writer_control.fixed_location
writer_control_write_base      => writer_address_base,     
writer_control_write_length    => std_logic_vector(to_unsigned(4, 32)),    
writer_control_go              => writer_go,        
writer_control_done            => writer_done,         
writer_user_write_buffer       => writer_write_buffer,       
writer_user_buffer_input_data  => writer_buffer_data, 
writer_user_buffer_full        => writer_buffer_full,     
--Writing process
writer:process(CLOCK_50)
begin
    if rising_edge(CLOCK_50) then
         if SW(1) = '0' then
            case transmit_state is
            when write_buffer =>
               if writer_buffer_full = '0' then
                   writer_write_buffer <= '1';
                   writer_go <= '1';
                    transmit_state <= writing_done;
               end if;
                    
            when writing_done =>
              writer_write_buffer <= '0';
              writer_go <= '0';
              if writer_done = '1' then
                  transmit_state <= writing_idle;
              end if;
                    
            when writing_idle =>
                null;
            end case;
         else
            transmit_state <= write_buffer;
                
            writer_write_buffer <= '0';
            writer_go <= '0';
                
            writer_address_base <= STD_LOGIC_VECTOR(to_unsigned(100 , 32));
            writer_buffer_data <= STD_LOGIC_VECTOR(to_unsigned(258076532 , 32));
         end if;
     end if;
end process writer;

I use a switch to perform one write at a time at a defined address. My first doubt is that the signal "writer_done" is never asserted.

Nevertheless, I can read the correct value at the written address (100) using my Nios program.

But when I'm trying to loop write (in the VHDL) and read values using my Nios program, it keeps on crashing and I can't figure out why. I'm assuming that trying to perform a nios read access while writing in the SDRAM put me in this situation but I don't know how to protect this situation from occuring.

Can you please help me ?

Thanks,

Nemesys

Altera_Forum · ‎09-29-2014

--- Quote Start ---

But when I'm trying to loop write (in the VHDL) and read values using my Nios program, it keeps on crashing and I can't figure out why. I'm assuming that trying to perform a nios read access while writing in the SDRAM put me in this situation but I don't know how to protect this situation from occuring.

--- Quote End ---

I guess the VHDL loop write is blocking some bus signal and prevents Nios from accessing sdram,

whilst using the test switch the same condition is momentary and you don't experience the problem.

Altera_Forum · ‎09-29-2014

Thanks for your reply.

Is there any way I can lock the Nios while I'm writing the SDRAM ? I tried to do it using shared IOs but I haven't been able to make it work since the Nios had to poll a signal (a thus access the SDRAM)...

Altera_Forum · ‎09-30-2014

I believe the problem is with your MM master device, rather than Nios.

Please clarify what you mean with "... when I'm trying to loop write (in the VHDL) ... "

Are you still using the switch to write data one by one? Or are you continuously pulsing writer_go signal?

Altera_Forum · ‎10-20-2014

Make sure that your Avalon MM master does not perform any accesses while the waitrequest signal is asserted. This is one of the most critical things with avalon masters

/Boris