Debugging Transceiver Links

[Altera_Forum]

Hi, I'm quartus II beginner. 

I want to modify the number of channels, bit rate, and clock in an Altera design example <transceiver_toolkit_13_0sp1_qar/ sv_4ch_32b_6445mbps>. so I added channels by creating more Avalon-ST Data Pattern Generator, checker, and other related IP Core and modified bit rate an clock and then generated modified v.file. And then compiled the files. However, channel manager in transceiver toolkit GUI shows still previous set-up. In other words, there is no added channel and bit rate and clock is same with before. I don't know how to update the transceiver links. How can I solve this problem?  Thanks.

[Altera_Forum]

I have changed these designs in the past, and here's the procedure I followed; 

 First I start with a standard design, and if required modify the pin assignments to match my specific hardware, synthesize and confirm there are no issues, eg., constrain any unconstrained paths (like JTAG). I then test this in hardware to confirm I have a known-good reference design. I'll then often change the data rate of the links for tests.  I then modify this known-good design. Eg., add new transceiver blocks, along with their data pattern generator and checker cores into Qsys, generate the new Qsys system, synthesize (to check it works), then using the Pin Planner I make the pin assignments, and re-run synthesis.  You did not comment about making pin assignments - did you make sure you updated those correctly?  The Transceiver Toolkit GUI is broken in 14.0. It does not work correctly. I have to delete the channels that it automatically creates, and then use the Setup button to create them. I then save that as a Tcl script and reload it next time I run the test.  I've been testing with Stratix IV and Arria V GZ devices. The Arria V GZ devices have the same transceiver IP as the Stratix V.  Your description above sounds correct. I don't see why you do not see the additional channels. I assume you downloaded the updated design?  Cheers, Dave

[Altera_Forum]

Thank you, Dave. I'm the colleague of Shin, and this is the errors I founded. 

Recently, I took this over from her, and tried to fix the pin planner also. The example file's nodes are located like this GXB_RXL11 - AA36 (B1L) GXB_RXL12 - Y38 (B2L) . . GXB_TXL11 - Y34 (B1L) . . . GXB_TXL14 - T34 (B2L)  Those locations are same with the fitter location. So, I placed channel 15~16 to the locations from reference manual, and I success the compile. But additonal channels doesn't appeared in console. What additional jobs required for this situation?

[Altera_Forum]

--- Quote Start ---   But additonal channels doesn't appeared in console. What additional jobs required for this situation?    --- Quote End ---   If the fitter results confirm you have the right number of channels, then the issue is probably just the Transceiver Toolkit GUI.  Click on the "Setup" button in the GUI and create the channels. You can save the setup as a Tcl script and load it next time you start the GUI.  If you are using 14.0, then delete all the existing channels and start from scratch. In the examples I tried, the GUI would not interface to the transceiver registers correctly using any of the default channels.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I've been using the Transceiver Toolkit with 14.0.0 build 200 in AVGZ and haven't seen any of the issues you're describing. While Altera hasn't updated the toolkit example designs in a while, you actually don't need any of the adapters anymore. In my Qsys system, I've got the tx and rx clock and data hooked up directly to the generator and checker blocks. I'm curious if that's causing the issues you're seeing with the auto detect? They appear as I'd expect when I launch the toolkit.  Hope this helps, Scott

[Altera_Forum]

Hi Scott, 

  --- Quote Start ---   I've been using the Transceiver Toolkit with 14.0.0 build 200 in AVGZ and haven't seen any of the issues you're describing. While Altera hasn't updated the toolkit example designs in a while, you actually don't need any of the adapters anymore. In my Qsys system, I've got the tx and rx clock and data hooked up directly to the generator and checker blocks. I'm curious if that's causing the issues you're seeing with the auto detect? They appear as I'd expect when I launch the toolkit.   --- Quote End ---   I'm pretty sure the failed auto-setup was with the examples provided for the TTK ... perhaps for the Stratix IV Development Kit (since I have one of those).  The Arria V GZ that I am using is on the Texas Instruments TSW14J56 development kit, so I had to modify the TTK examples to support that kit. I think that failed too. I've got some notes around here that I need to turn into a PDF :)  I recall one of the issues being that the GUI would show the channels correctly, but would not allow you to change the pattern generator/checker patterns.  To compound the difficulty with using the TTK, the Native PHY setup I needed for my tests is not supported by the Qsys Custom PHY IP (or whatever its called), so I needed to create my Qsys system with the pattern generator and checker, but no PHY interface that was recognizable by the TTK. In this case, its still possible to use the TTK for eye-pattern sweeps etc (via the Reconfig controller), but the loopback checkbox does not work (I have a separate register to turn that on).  A lot of the TTK PHY components are not officially supported. Eg., if you try to create an instance of a core used in the examples, that core does not exist in the Qsys components menu. If you look in the _hw.tcl file for the components used in the example, their visibility is set to FALSE. You have to change that to TRUE and regenerate the .ipx file in the Quartus installation to make it visible. At that point, you can create a new Qsys system and add the various PHY IP components. Without changing the visibility, you can only copy-and-paste an existing Qsys system to create a new system.  TTK is nice, but its hardly a "completed" product :)  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I definitely agree on it not being completely fleshed out. I had a fair amount of pain myself using it in Stratix IV. I recall the .ipx issue as well and wasn't too pleased that SIV was left unsupported. Now that I'm in AVGZ, I'm finally getting to take advantage of the improvements.  For AVGZ, I'm using the low latency PHY for hardware eval. In this case, I pretty much gutted the example design. The loopback and pattern generator/checker (with bypass) pieces are working for me. I believe Native PHY is supported for the toolkit directly as well. I've attached my qsys system as a txt file in case you're interested.  Scott

[Altera_Forum]

Hi Scott, 

 Thanks for your example design!  Do you happen to have some measurement data on your 12G links? I have some test eye-pattern scans in this PDF ...  http://www.ovro.caltech.edu/~dwh/correlator/pdf/hawkins_jpl_2014.pdf  p25 has a picture of the ADC board I am worked on (with 10Gbps outputs), pp36 to 42 has transceiver link tests. These results were not optimized, i.e., no transmitter pre-emphasis or receiver equalization. I wanted to start with a "reference" data set. I'm in the process of writing my own eye-pattern sweep, since I wanted to be able to control the logic behind the eye-pattern generation.  I'm interested in hearing if you have a custom designed board, and what it took to get your links working nicely at 12Gbps. I plan on designing a Stratix V or Arria V GZ with as many QSFP+ connectors as I can, so I'm interested in understanding where others have succeeded :)  Cheers, Dave