Best way to define a clock for TimeQuest analysis

[Altera_Forum]

I have a logic design for a CPLD where a clock goes out on a device pin, and comes back in on another device pin with a fixed delay (say, 10 ns). 

 How can I best describe the incoming clock to TimeQuest, without losing the relationship to the outgoing clock ? I guess a virtual clock is out of the question, because it loses exactly that relationship. So should it be defined as a generic clock (which, by default, will relate it to its source, although I'm not entirely sure what that means in practice) ? Or as a generated clock (incoming = outgoing + 10 ns delay) ? Or is it impossible to keep the relationship available to the analysis ?  Any (informed) hints appreciated.   John Kortink Windfall Engineering

[Altera_Forum]

You have to put a generated clock on the output, one on the input, and then use set_clock_latency to connect them. Something like the following: 

 create_clock -period 14.286 -name fpga_clk_in [get_ports fpga_clk_in]  derive_pll_clocks # create_generated_clock -source {inst|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {inst|altpll_component|auto_generated|pll1|clk[1]} {inst|altpll_component|auto_generated|pll1|clk[1]} # create_generated_clock -source {inst|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {inst|altpll_component|auto_generated|pll1|clk[0]} {inst|altpll_component|auto_generated|pll1|clk[0]}  create_generated_clock -source inst|altpll_component|auto_generated|pll1|clk[1] -name sdram_clk [get_ports sdram_clk]  create_generated_clock -source [get_ports sdram_clk] -name fedback_clk [get_ports fedback_clk]  set_clock_latency -source -late 10.0 [get_ports fedback_clk] set_clock_latency -source -early 6.0 [get_ports fedback_clk]

[Altera_Forum]

Very useful. Thanks.

[Altera_Forum]

Hi rysc, how can I send a message to you? alteraforum informs me that you can't receive private messages.