How to replace undefined entities with black boxes?

[Altera_Forum]

Hi, 

 I have a part of a big project and want to see graphical view of the netlist. For this purpose I'm going to do "Analysis & Elaboration" and then use "RTL Viewer" to analyse netlist. But as I said I have only part of this project. And during "Analysis & Elaboration" I get 1.3k errors similar to this:  12006 Node instance "yyy" instantiates undefined entity "xxx"  This entities are not important for me. Only nets are interesting. Are there any settings in Quartus that allow to replace these entities with black boxes and ignore them?

[Altera_Forum]

--- Quote Start ---  Hi,  I have a part of a big project and want to see graphical view of the netlist. For this purpose I'm going to do "Analysis & Elaboration" and then use "RTL Viewer" to analyse netlist. But as I said I have only part of this project. And during "Analysis & Elaboration" I get 1.3k errors similar to this:  12006 Node instance "yyy" instantiates undefined entity "xxx"  This entities are not important for me. Only nets are interesting. Are there any settings in Quartus that allow to replace these entities with black boxes and ignore them?  --- Quote End ---    For P&R and timing a blackbox is confusing! as the drives are not available For a taste of P&R I will just drive blackbox outputs with some constants. I don't know if some attributes can just do that.

[Altera_Forum]

--- Quote Start ---  For P&R and timing a blackbox is confusing! as the drives are not available For a taste of P&R I will just drive blackbox outputs with some constants. I don't know if some attributes can just do that.  --- Quote End ---   I don't need P&R. Only "Analysis & Elaboration" is necessary

[Altera_Forum]

To black-box a hierarchy you still need something to describe it. For example, if I had a module called blaa, I might have a verilog file that says: 

module blaa ( input clk, din, a,b,c; output d,e,f); endmodule  Note that there are no contents, just the port listing. For VHDL I do something similar and just have it empty between architecture:  ARCHITECTURE empty OF top IS BEGIN END empty;  That should be enough to get it through analysis and elaboration(and synthesis). A nice trick to get it through the fitter is to run Hierarchy Elaboration, then put all those hierarchies into partitions and set them to Empty. This prevents synthesis across boundaries so anything hooked up to these black-boxes doesn't get synthesized out and you can analyze the rest of the design. (This is a nice trick for faster compiles too, i.e. I might have a large design and the full project, but I only care about a particular hierarchy. Rather than making a new project and trying to convert the timing constraints, etc., I just select a few large hierarchies I don't care about and put them into Empty Partitions. The fitter no longer has to place-and-route them and can quickly fit the parts I care about.)

[Altera_Forum]

--- Quote Start ---  To black-box a hierarchy you still need something to describe it. For example, if I had a module called blaa, I might have a verilog file that says: module blaa ( input clk, din, a,b,c; output d,e,f); endmodule  Note that there are no contents, just the port listing. For VHDL I do something similar and just have it empty between architecture:  ARCHITECTURE empty OF top IS BEGIN END empty;  That should be enough to get it through analysis and elaboration(and synthesis). A nice trick to get it through the fitter is to run Hierarchy Elaboration, then put all those hierarchies into partitions and set them to Empty. This prevents synthesis across boundaries so anything hooked up to these black-boxes doesn't get synthesized out and you can analyze the rest of the design. (This is a nice trick for faster compiles too, i.e. I might have a large design and the full project, but I only care about a particular hierarchy. Rather than making a new project and trying to convert the timing constraints, etc., I just select a few large hierarchies I don't care about and put them into Empty Partitions. The fitter no longer has to place-and-route them and can quickly fit the parts I care about.)  --- Quote End ---   Thank you. I hoped that it will require less efforts :)