Cyclone V SOC GPIO test by register access

[Altera_Forum]

Hello together, 

for a simple hardware test I want to set/clear a HPS GPIO pin by writing values into the corresponding registers. I have activated GPIO00 in QSYS and in Quartus connected with a top level signal. The fitter assigns the correct pin automatically (Pin E4 in a Cyclone V SE with 672 pins). Linux is running after startup and via console I made the following register settings: (0xffd08400) = 0x00000000 (EMACIO0, multiplexer setting for GPIO/LoanIO) (0xffd085d4) = 0x00000001 (GPLMUX0, multiplexer setting for GPIO0) (0xff708004) = 0x00000001 (GPIO0 data direction as output) Now I expected to set / clear the pin via register 0xff708000 / bit 0. But the pin remains in high ohmic state. What did I forget to do?  Quartus Version 14.0 Device 5CSEBA5U23I7N

[Altera_Forum]

You shouldn't have to write to those registers, the 2nd stage bootloader handles this automatically because it uses handoff information passed to it to configure all the pin multiplexing during the boot process. At first glance it looks like you configured the registers correctly but I would just let the bootloader do these steps for you.

[Altera_Forum]

Yes, after generating a new preloader and replacing the old by the new one it works. 

Thanks for your response and best regards