connecting onchip memory or SDRAM to the HPS using HPS to FPGA bridge

[Altera_Forum]

Hello,  

 I am using the Terasic DE1-SoC board with the Linux LXDE example as a base. For a project I need to transfer about 10Myte/sec of data from the FPGA to the HPS. If possible I want to use the 64Mbyte SDRAM connected to the FPGA, the FPGA places the data inside it and the HPS onlu needs to read it out. To get something small working I started with some on chip memory. In Qsys I added 32Kbyte 32bit wide on chip memory and connected this to the lightweigth bridge.  And after a bit of experimenting in Linux with the C code it works :) I can write data to it and read it back in, all in linux running on the HPS.  If I connect it to the normal HPS to FPGA bridge instead of the lightweight bus things go quite wrong :( I used 0xc000_0000 instead of 0xff20_0000 as offset but when I try to write 32K of data to it the whole system just crashes :( Is there anything else I need to fo differently when using the HPS to FPGA bridge instead of the LW one except the offset change?  I eventually want to use the SDRAM on the FPGA instead of the on chip memory. Is it possible to connect it to the HPS to FPGA bridge and read the content of it in Linux on the HPS? I only need to read it, read/write would be nice but isnt essential.  Or am I looking at it in a wrong point of view and are there better ways to send data from the FPGA to the HPS? I looked at writing data to the HPS DDR3 like used here: https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/writing_to_hps_memory But after mailing Terasic I learned that their Uboot isnt open source so it seems that I can't add the MEM=512M flag, making that example impossible :( I am quite new to the FPGA + HPS idea and have some experience in VHDL and Linux but not really in building a linux distro for an embedded platform.  Best regards,  Rik

[Altera_Forum]

Yes, the HPS can access a memory connect/in the FPGA by accessing it through the HPS-to-FPGA bridge assuming your FPGA design has it hooked up. Make sure that the bridge is clocked, pulled out of reset, and is mapped into the address space (remap bit in the L3 interconnect registers). 

 Since you said "FPGA to the HPS" for the data movement it might make more sense for the FPGA to push data into the HPS SDRAM directly using the FPGA-to-SDRAM ports instead. You could pin a continuous memory block in the HPS SDRAM and then just tell the FPGA where it lives and let FPGA masters push the data into it (DMA).

[Altera_Forum]

--- Quote Start ---  Yes, the HPS can access a memory connect/in the FPGA by accessing it through the HPS-to-FPGA bridge assuming your FPGA design has it hooked up. Make sure that the bridge is clocked, pulled out of reset, and is mapped into the address space (remap bit in the L3 interconnect registers).  Since you said "FPGA to the HPS" for the data movement it might make more sense for the FPGA to push data into the HPS SDRAM directly using the FPGA-to-SDRAM ports instead. You could pin a continuous memory block in the HPS SDRAM and then just tell the FPGA where it lives and let FPGA masters push the data into it (DMA).  --- Quote End ---    Hi BadOmen, I'm trying to understand how the approach you suggested works. Could you please give me any explanation?  In my project I need to transfer data from HPS to FPGA and conversely and the DMA approach should be the best.  Thank you in advance for any advice!

[Altera_Forum]

Hello, 

Did you figure out a way around the problem? I'm trying to do something similar... Maybe you can help. I want to write data into SDRAM (or any memory for that matter) which is then read by FPGA. After processing, it writes back to a memory space from where the HPS reads these 'FPGA results'.  For now I have a SDRAM controller in my Qsys design (base address 0x0800_0000).  So to write from the HPS I use the lw bridge? For example:  alt_write_word(lw_bridge_map+ SDRAM_BASE_ADDRESS ,0x50);  Is this the right way to do it? Then how do I access this newly written data from the FPGA?  Your thoughts would be appreciated.  Thanks.

[Altera_Forum]

Hiii 

 Can you explain to me more why this example is impossible:cry: I was triying to let the exapmle works on my DE1-SOC board for 2 month:( :(  "I looked at writing data to the HPS DDR3 like used here: https://support.criticallink.com/red..._to_hps_memory (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/writing_to_hps_memory) But after mailing Terasic I learned that their Uboot isnt open source so it seems that I can't add the MEM=512M flag, making that example impossible :("