DDR3 memory controller in Cyclone V

[Altera_Forum]

Hi, I am new to DDR3 memory controller design. I have a cyclone V development board. I fired up the IP tool and generated a DDR3 controller. This is whwer I am having a problem. How do I interface the AVL signals to the rest of my system? I have been digging around the internet, and it looks like I need logic to go from 64 bits(controller) to 16 bits (my logic). To further complicate matters, there is no good documentation on how to do this.

[Altera_Forum]

I posted a DDR3 example for the BeMicro-CV board in this thread - scroll down to Post#5 

 http://www.alteraforum.com/forum/showthread.php?t=43992  The DDR3 controller is intended to be used from a Qsys system. You could use it standalone, but generally its easier to build your own custom logic as an Avalon-MM master or slave and then integrate it using Qsys. Yeah, this seems daunting to start with, but its worth the effort. If you get stuck, members of the forum will help you.  Cheers, Dave

[Altera_Forum]

Thanks Dave.