Propagation Delay for SPI bus routed through MAX II CPLD

[Altera_Forum]

Hello All, 

 I have a question regarding routing an SPI bus through a MAX II CPLD. I am using the set_max_delay to constrain the pin to pin delay on the SPI lines (MISO,MOSI,CLK,CSN), but I have been unable to get the propagation delay below 6-7ns, even when selecting adjacent pins on the package.  For example, here is the timequest report on a test path between two signals (DMAG1 to SPIF2_DI). Note, there is no combinational logic placed between these pins in the VHDL, only an assignment statement (SPIF2_DI <= DMAG1).http://www.alteraforum.com/forum/attachment.php?attachmentid=9928&stc=1   Does anyone have any suggestions on how to get this delay down? The SPI clock is 50 MHz, so I really only have a few ns to spare in CPLD propgation delays. The MAX II handbook mentions a fast I/O connection between adjecent LAB and IOE but I am not quite sure how to exploit this.

[Altera_Forum]

If you use registers in your vhdl/verilog then you might try the fast input/output register option in the assignment editor for the relevant IO pins to improve timing.