SDRAM to run code / Symptoms off an untuned PLL

[Altera_Forum]

Good morning, we're currently working on a custom made board. It features a 32MB SDR SDRAM (IS42S16160G-6TLI) and a Cyclone III EP3C25Q24. We're trying to make it work with a NIOS II processor which has an SDRAM Controller configured in QSys to match Data Width, Architecture and Address Width. We can write data to the DRAM memory through code running from on-chip memory, but whenever the code is located on the SDRAM the system cannot run and debugger doesn't start. 

 Reading the SDRAM Controller Core section in Embedded Peripheral IP User Guide http://www.altera.com/literature/ug/ug_embedded_ip.pdf , I found out about the possibility of an Untuned PLL and that the symptoms were similar in our application.  The Embedded Peripheral UG recommends several things and from here is where I find difficulty in following the guide:  1) The user guide states that the pins involved should be assigned as Fast Output (or input) registers to minimize delay. This we thought that it was done already but at the end of compilation inside the Ignored assignments section I find things like> Name:Fast Input Register, Ignored Entry: Prueba1Qsys_SDRAM, Ignored from (blank), Ignored to: za_data[0]~reg0, Ignored Value: ON, Ignored Source: Compiler or HDL Assignment. Also, how should I assign this for bi-directional pins (Data pins for SDRAM)?  Could someone explain how to do this assignments? I found another document from altera stating a list o things that could have gone wrong but I'm a beginner so I don't really get it. I'd find more useful a series of practical instructions to follow on how to check what has gone wrong.  2) The Emb Peripheral UG states that one should check the " ...the relevant timing information, obtained from the Timing Analyzer section of the Quartus II Compilation Report. The values in the table are the maximum or minimum values among all device pins related to the SDRAM." And then it shows a table of values . I understand that there is a section for TimeQuest Timing Analizer once the project is compiled but have none of experience on this, and I can't find any information in there regarding the pins connected with the SDRAM. Could someone point me out a document or tutorial in using this feature? where to find the Tco (clock-to-output time), TH (hold time after clock) and TSU (setup time before clock) for these signals or how to generate them. Just where to start.  Apart from the internal delays of my FPGA i understand that I should also take into account the delays caused by the propagation delay on the PCB, but this is another story as I have previously used a signal integrity simulator and have IBIS models to run a simulation and obtain data (am more of a circuit design/PCB designer).  Later on, the document makes some additions and substractions on the data to find the window inside which the clock may be shifted, and calculates the mid-point of this. It seems simple once you have the data, the problem is this document doesn't give me any directions to find these values.   I hope I was clear enough about the problems, please let me know if I can provide further details. Thanks.