DE0-Nano Ethernet add on board

[Altera_Forum]

Dear all 

  I'm student of electrical engineering in university of tehran. Recently i designed an add on board for DE0-Nano board which provide it Ethernet interface.  http://www.alteraforum.com/forum/attachment.php?attachmentid=10012&stc=1      I have used DM9161AEP as a physical layer and connected it to Altera TSE MAC layer (small 10/100 MAC) via MII interface. after creating essential system in Qsys (according to 'using_triple_speed_ethernet.pdf') and testing system, a strange problem appeared! When i connect my board to PC via CAT5 cable and send some string (in jtag_uart console), the TX path of system (form board to PC) works fine. and i can see that a LLC packet received by my PC (watching packets in wireshark). but nothing is received! in other word, RX path of board does not work correctly.  here is snapshot of wireshark and Nios2 console that show successful transmission of LLC packet: http://www.alteraforum.com/forum/attachment.php?attachmentid=10015&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=10016&stc=1   For ensuring of PHY layer, i use a SignalTap II logic analyzer in RX pins. (RX_DATA,RX_DV,RX_ERR,RX_CLK)  every things is good! i can see digital data receied by PYH (which sent form my PC) and match them by packet i saw in wireshark! It's amazing!  here is snapshot of SignalTap II logic analyzer that show received ARP packet by PHY layer: http://www.alteraforum.com/forum/attachment.php?attachmentid=10017&stc=1    Now,i know that PYH layer is working correctly and there is problem in connection of PHY to MAC in RX path. but i can't understand what is this problem! help me please. this project is very important to me. (if needed, i can provide you project files like Schematics, Quartus project and any other files)   Regards, Arash

[Altera_Forum]

I may be doing it wrong, but your screenshots are too low resolution to read. 

 You may need to post your project .qar   Your problem might be something simple like incorrect TSE MAC port pin connections, or a clock issue. Quartus might already be complaining about the cause of your problem: check your warnings, and timing violations (if any).

[Altera_Forum]

Dear ted, 

thanks for repaly. I have attached some pictures in '.zip' format and my '.qar' project file. https://www.alteraforum.com/forum/attachment.php?attachmentid=10023  https://www.alteraforum.com/forum/attachment.php?attachmentid=10024  I hope them to be useful. But about inter-connect of PHY and MAC. I test similar configuration in DE2-115 board which inculde Marvell 88E1111 PHY layer. (Samll TSE MAC that connect to PHY via MII interface) every things works fine! I ran simple socket server example on DE2-115 board and it was very interesting. but i can't understant what is this problem that only appear in RX path not on TX path!  thanks for your attention Arash

[Altera_Forum]

Briefly reviewing your Qsys/Quartus project, it all looks OK and your SignalTap does seem to be showing a packet coming in. 

At this point I'm guessing there is a bug in your .c somewhere.  You can double check with SignalTap that the Avalon-ST ports to/from the SGDMA are OK - they ought to be 'ready' and maybe you'll see 'sop' ?  I would also suggest during this debug phase to switch over to the full 10/100/1000 MAC so you can incorporate and dump the statistics counters. If you're seeing data coming in on the PHY, and nothing on the Avalon-ST - you ought to see some counters increment.

[Altera_Forum]

Dear ted, 

Thanks for replay and tips. I will check them all.  Thanks for your attention and time you spent on this topic. Arash

[Altera_Forum]

Dear ted, 

 As you suggest, i use 10/100/100 TSE MAC core and check statistics counters. for more simpler test, i enabled loop-back feature of MAC core. But another confusing problem appeared! When i send a string vi jtag_uart, 'aFramesTransmittedOK' increament by one but 'aFramesReceivedOK' stay 0. More intresting is that register 'aFrameCheckSequenceErrors' and 'aAlignmentErrors', both increament in each of my send! I'm just working in loop back mode! why should i have CRC/Alignment error?  In real test with PHY, as picture of wireshark showed, i'm sure that TX path of system works correctly. Now the statistics counters of MAC showed that packet are received with CRC/Alignment error. Do you have any idea?  Thanks.

[Altera_Forum]

I think you can get that behavior with wrong setting of the 32-bit header alignment option in the MAC. 

Search for "align" in http://www.altera.com/literature/ug/ug_ethernet.pdf  I believe the checkbox is on the MAC Options tab of the gui: change it from what it is currently set to, and try again.

[Altera_Forum]

Dear ted, 

thanks for replay.  I checked MAC option about 32 bit header alignment. and test system in both situation. (select and un-select alignment in MAC option) but nothing changed! I also removed the two first byte of tx_frame in c source code. (which is used for 32 bit alignment). Again i just see that register 'aFrameCheckSequenceErrors' and 'aAlignmentErrors' increment in each send when i'm in loop back mode.

[Altera_Forum]

Dear all 

I use another idea to detect the problem of RX path in my system. this is main connection of PHY and MAC in my system:   .tse_mac_pcs_mac_tx_clock_connection_clk (TXCLK),   .tse_mac_pcs_mac_rx_clock_connection_clk (RXCLK),   .tse_mac_mac_mii_connection_mii_rx_d (RXD),   .tse_mac_mac_mii_connection_mii_rx_dv (RXDV),   .tse_mac_mac_mii_connection_mii_rx_err (RXERR),   .tse_mac_mac_mii_connection_mii_tx_d (TXD),   .tse_mac_mac_mii_connection_mii_tx_en (TXEN),   .tse_mac_mac_mii_connection_mii_tx_err (TXERR),  and i changed it to :   .tse_mac_pcs_mac_tx_clock_connection_clk (RXCLK), <--  .tse_mac_pcs_mac_rx_clock_connection_clk (RXCLK),   .tse_mac_mac_mii_connection_mii_rx_d (TXD), <--  .tse_mac_mac_mii_connection_mii_rx_dv (TXEN), <--  .tse_mac_mac_mii_connection_mii_rx_err (RXERR),   .tse_mac_mac_mii_connection_mii_tx_d (TXD),   .tse_mac_mac_mii_connection_mii_tx_en (TXEN),   .tse_mac_mac_mii_connection_mii_tx_err (TXERR),  it's just a loop-back idea. MAC receive what it sent! but it's based on RXCLK. this test was successful and loop-back worked correctly. so i'm sure that MAC works fine! now I'm sure that problem is in connection of MAC and PHY in RX path. but I don't understand it. (it seems that MAC detect RXCLK but do not detect RXD and RXDV) if there is problem in RX connection (PCB or Header pins) why Logic analyzer can detect RX signal? but MAC can not ??! is there any other setting for FPGA pin that I missed?

[Altera_Forum]

No idea ??! 

It's very important for me ...